MLIN
C3
Figure 29. Schematic of Example
Application Circuit.
At the RF input port, series
capacitor C1 and transmission line
MLIN form the input matching
network and high pass filter.
(Note: The PCB layout above has
provision for an inductor, L1, in
series with MLIN. Inductor L1 is
not used in this design.)
Referring to the table of Reflec-
tion Coefficients, the RF input
port
Γ
RF
= 0.82
∠−37°
at 1.9 GHz.
This point is plotted as Point A on
the Smith chart in Figure 30. For
reasons previously discussed in
the “RF Port” section above, a
series C - shunt L network (from
the 50
Ω
source to
Γ
RF
) will be
used to match
Γ
RF
to 50
Ω.
Addition of a 6.5 nH shunt induc-
tance moves the impedance
trajectory from Point A to Point B.
The match to 50
Ω
is completed
with a 0.6 pF series capacitance,
C1, that moves the match to
Point C, the center of the Smith
chart.
1
0.5
2
LO
H
RF
IF
+V
IAM-91
Figure 28. PCB Layout.
1.9 GHz Design Example
To illustrate a design approach for
using the IAM-91563, a PCS band
downconverter with an RF of
1.9 GHz and IF of 110 MHz is
presented. The PCB layout above
was used to assemble the mixer
and verify performance.
A schematic diagram of the
1.9 GHz circuit is shown in
Figure 29.
0.2
0.2
C
-0.2
0.5
B
A
RF C1
Input
-0.5
-1
Figure 30. RF Input Impedance
Match.
91
Application Example
The printed circuit layout in
Figure 28 is a general purpose
layout that will accommodate
components for using the
IAM-91563 for RF inputs from
800 MHz to 6 GHz. This layout is a
microstripline design (solid
groundplane on the backside of
the circuit board) with 50
Ω
interfaces for the RF input, IF
output, and LO input. The circuit
is fabricated on 0.031-inch thick
FR-4 dielectric material. Plated
through holes (vias) are used to
bring the ground to the top side of
the circuit where needed. Multiple
vias are used to reduce the
inductance of the paths to ground.
LO
Input
RF
Input
C7
C1
L1 = 0
L3
RFC
L2
C2
C4
C5
C6
IF
Output
V
d
For this example, the shunt
inductor was realized with the
transmission line, MLIN in Fig-
ure 29 ( Z
O
= 90
Ω,
length =
0.35 in.). A high quality capacitor
should be selected for C1 to
minimize the effects of the
capacitor’s parasitic inductance
and resistance. Series capacitor
C1 also serves to block any DC
that may be present at the output
of the stage preceding the mixer.
At the IF output, the low pass
filter and impedance match is
formed by shunt capacitor C2 and
series inductor L2. Referring again
to the table of Reflection Coeffi-
cients, the IF output port
Γ
IF
=
0.64
∠
-8° at 100 MHz, which is the
frequency point closest to the
desired IF of 110 MHz.
Γ
IF
is
plotted as Point A in Figure 31.
1
0.5
A
0.2
C2
B
L2
C
IF
Output
2
0.2
0.5
1
C
2
A
B
-0.2
-0.5
-1
-2
Figure 31. IF Input Impedance Match.
B
1
C
2
Adding a shunt capacitance (C2)
of 11.3 pF brings the impedance to
Point B. The match to Point C at
the center of the chart is com-
pleted with a series inductance
(L2) of 150 nH.
Although not necessary for many
applications, the match at the LO
port can be improved by the
addition of series inductor L3 with
a value of approximately 8 nH.
Design information (Γ
LO
) for
matching the LO port is obtained
L
A
-2
7-144
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
