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HPMX-5001 参数 Datasheet PDF下载

HPMX-5001图片预览
型号: HPMX-5001
PDF下载: 下载PDF文件 查看货源
内容描述: 1.5-2.5 GHz的上变频/下变频 [1.5-2.5 GHz Upconverter/ Downconverter]
分类和应用: 射频和微波射频上变频器射频下变频器微波上变频器微波下变频器
文件页数/大小: 15 页 / 171 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Transmit Mode
For transmit upconversion, a
differential narrow-band
modulated signal is AC-coupled
into the TXIF and TXIFB inputs.
The differential signal may be
generated by the HPMX-5002 IF
Demodulator/Modulator. Once
on-chip, the signal is buffered and
applied to a double-balanced
Gilbert cell mixer. The
upconverted RF signal is then
amplified to generate a -0.6 dBm
single-ended, single-sideband
power signal at the 1 dB
compression point. The RF
outputs, TXRF and TXRFB, are
open-collector outputs (see test
diagram Figure 28 for recom-
mended matching network). The
TXRF output is AC-coupled into a
50
transmit filter. This signal is
then filtered and amplified off-
chip by an external power ampli-
fier before it is switched into the
antenna. The HPMX-5001 may
also be used in DECT systems
which utilize direct modulation of
the 1LO for data transmission. In
this case, either the TXIF or
TXIFB input, but not both, must
be tied to V
CC
to cause the
upconverting mixer to act as a
buffer stage.
Receive Mode
In receive mode, a preamplified
RF signal is passed through an
image filter and applied as a
single-ended signal to the 50
RXRF input. Use of a 2.7 pF
blocking capacitor is recom-
mended. RXRF is the non-
inverting input of the RF input
amplifier. The inverting input of
this amplifier, LNAREF, is self-
biased and requires only an
external capacitor (recommended
value of 3.3 pF) to ground. The
receive downconversion mixer
also employs a double-balanced
Gilbert cell configuration. The
production version of the
HPMX-5001 will have two
equivalent open collector outputs.
The HPMX-5001 can operate at IF
frequencies up to 300 MHz (see
Figure 28 for recommended
matching network).
Synthesizer Mode
The on-chip 32/33 dual-modulus
prescaler, in conjunction with the
VCO, external tank circuit, and
CMOS synthesizer, form a phase-
locked loop (PLL). The prescaler
divider output and modulus
control input are designed to be
compatible with positive-edge
triggered CMOS synthesizers
from a variety of vendors. The
timing requirements for the
prescaler are shown in Figure 2.
It is important to note that the
prescaler divides the VCO signal,
and not the frequency doubler
output. Local oscillator (LO)
signal generation on the
HPMX-5001 is accomplished
through the combination of a
VCO and frequency doubler. The
VCO is a simple Clapp oscillator
for the best possible noise
performance. The VCO force and
sense pins (VCOTNKF,
VCOTNKS) are self-biased, so
that the connections to the tank
(minimum Q of 20) are through
AC-coupling capacitors.
VCOTNKS can also be used with
an injected LO. VCOTNKF would
then be left floating. The doubler
circuit multiplies the VCO
frequency by two. This enables
the VCO to have lower sensitivity
to both package parasitics and LO
re-radiation. Separate bias pins
and buffering are utilized to
minimize pulling of the VCO
when the chip is switched from
synthesizer to transmit or receive
mode.
7-102