5
AC Timing Characteristics over Temperature Range
V
DD
= 4.5 to 5.5 V unless otherwise specified.
Reference
Number
1
Symbol
t
ACC
Description
Display Access Time
Write
Read
Address Setup Time to Chip Enable
Chip Enable Active Time
[2, 3]
Write
Read
Address Hold Time to Chip Enable
Chip Enable Recovery Time
Chip Enable Active Prior to Rising Edge of
[2, 3]
Write
Read
Chip Enable Hold Time to Rising Edge of
Read/Write Signal
[2, 3]
Write Active Time
Data Valid Prior to Rising Edge of Write Signal
Data Write Hold Time
Chip Enable Active Prior to Valid Data
Read Active Prior to Valid Data
Read Data Float Delay
Reset Active Time
[4]
Min.
[1]
210
230
10
140
160
20
60
140
160
0
100
50
20
160
75
10
300
Units
ns
ns
2
3
t
ACS
t
CE
ns
ns
ns
4
5
6
t
ACH
t
CER
t
CES
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
9
10
11
12
13
t
CEH
t
W
t
WD
t
DH
t
R
t
RD
t
DF
t
RC
Notes:
1. Worst case values occur at an IC junction temperature of 125°C.
2. For designers who do not need to read from the display, the Read line can be tied to V
DD
and the Write and Chip Enable lines can be
tied together.
3. Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM,
regardless of the logic levels of the WR and RD lines.
4. The display must not be accessed until after 3 clock pulses (110
µs
min. using the internal refresh clock) after the rising edge of the
reset line.
Symbol
F
OSC
F
RF[5]
F
FL[6]
t
ST[7]
Notes:
5. F
RF
= F
OSC
/224.
6. F
FL
= F
OSC
/28,672.
7. t
ST
= 262,144/F
OSC
.
Description
Oscillator Frequency
Display Refresh Rate
Character Flash Rate
Self Test Cycle Time
25
°
C Typical
57
256
2
4.6
Minimum
[1]
28
128
1
9.2
Units
kHz
Hz
Hz
sec
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