14
Self Test Function (Bits 5, 6)
Bit 6 of the Control Word Register
is used to initiate the self test
function. Results of the internal
self test are stored in bit 5 of the
Control Word. Bit 5 is a read only
bit where bit 5 = “1” indicates a
passed self test and bit 5 = “0”
indicates a failed self test.
space (20H) will be loaded into
the Character RAM to blank the
display. The Flash RAM and
Control Word Register are loaded
with all “0”s. The UDC RAM and
UDC Address Register are
unaffected. All displays which
operate with the same clock
source must be simultaneously
reset to synchronize the Flashing
and Blinking functions.
Clear Function (Bit 7)
Bit 7 of the Control Word will
clear the Character RAM and the
Flash RAM. Setting bit 7 to a “1”
will start the clear function. Three
clock cycles (110 ms minimum
using the internal refresh clock)
are required to complete the clear
function. The display must not be
accessed while the display is
being cleared. When the clear
function has been completed, bit
7 will be reset to a “0.” The ASCII
character code for a space (20H)
will be loaded into the Character
RAM to blank the display and the
Flash RAM will be loaded with
“0”s. The UDC RAM, UDC
Setting bit 6 to a logic 1 will start
the self test function. The built-in
self test function of the IC
Mechanical and Electrical
Considerations
consists of two internal routines
which exercise major portions of
the IC and illuminate all of the
LEDs. The first routine cycles the
ASCII decoder ROM through all
states and performs a checksum
on the output. If the checksum
agrees with the correct value, bit
5 is set to “1.” The second routine
provides a visual test of the LEDs
using the drive circuitry. This is
accomplished by writing
The HDSP-210X/-211X/-250X are
28 pin dual-in-line packages with
26 external pins. The devices can
be stacked horizontally and verti-
cally to create arrays of any size.
The HDSP-210X/-211X/-250X are
designed to operate continuously
from -45°C to +85°C with a
Address Register, and the re-
mainder of the Control Word are
unaffected.
Display Reset
maximum of 20 dots on per
Figure 7 shows the logic levels
needed to Reset the display. The
display should be Reset on
character at 5.25 V. Illuminating
all thirty-five dots at full bright-
ness is not recommended.
checkered and inverse checkered
patterns to the display. Each
pattern is displayed for approxi-
mately 2 seconds.
Power-up. The external Reset
clears the Character RAM, Flash
RAM, Control Word and resets
the internal counters. After the
rising edge of the Reset signal,
three clock cycles (110 µs
minimum using the internal
refresh clock) are required to
complete the reset sequence. The
display must not be accessed
while the display is being reset.
The ASCII Character code for a
The HDSP-210X/-211X/-250X are
assembled by die attaching and
wire bonding 280 LED chips and
a CMOS IC to a thermally
conductive printed circuit board.
A polycarbonate lens is placed
over the PC board creating an air
gap over the LED wire bonds. A
protective cap creates an air gap
over the CMOS IC. Backfill epoxy
environmentally seals the display
package. This package
During the self test function the
display must not be accessed. The
time needed to execute the self
test function is calculated by
multiplying the clock period by
262,144. For example, assume a
clock frequency of 58 KHz, then
the time to execute the self test
function frequency is equal to
(262,144/58,000) = 4.5 second
duration.
construction makes the display
highly tolerant to temperature
cycling and allows wave
At the end of the self test func-
tion, the Character RAM is loaded
with blanks, the Control Word
Register is set to zeros except for
bit 5, the Flash RAM is cleared,
and the UDC Address Register is
set to all ones.
soldering.
The inputs to the IC are protected
against static discharge and input
current latchup. However, for
best results standard CMOS
Figure 7. Logic Levels to Reset the
Display.
handling precautions should be
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