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HDMP-1685A 参数 Datasheet PDF下载

HDMP-1685A图片预览
型号: HDMP-1685A
PDF下载: 下载PDF文件 查看货源
内容描述: 安捷伦HDMP - 1685A 1.25 Gbps的四通道的SerDes与5针DDR SSTL_2并行接口 [Agilent HDMP-1685A 1.25 Gbps Four Channel SerDes with 5-pin DDR SSTL_2 Parallel Interface]
分类和应用: 电信集成电路电信电路双倍数据速率
文件页数/大小: 20 页 / 292 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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HDMP-1685A Timing Characteristics – Transmitter Sections
T
A
= 0°C to T
C
= 85°C, V
CC
= 3.15 V to 3.45 V
Symbol
t
TXCT[2]
t
TXCV[2]
t_txlat
[1]
Parameter
TX [0:3][0:4] Input Data and TC Clock Transition Range
TX [0:3][0:4] Input Data and TC Clock Valid Time
Transmitter Latency
Units
ps
ps
ns
bits
2400
4
5
Min.
Typ.
Max.
1600
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the leading edge of the first half of a parallel 10-bit word and the
leading edge of the first transmitted serial output bit of that 10-bit word.
2. Agilent‘s HDMP-1685A internally generates another clock which is 90 degrees out of phase with the TC clock supplied. This clock, which will
have its edges at the center of the data valid eye, is used to clock in the TX[0:4] data. Setup and hold times are taken care of by the
HDMP-1685A provided the specifications indicated are met.
8 ns
TXCT
TX[0:3][0:4]
TXCV
TXCV
TC
Figure 3. Transmitter section parallel input timing.
10-BIT CHAR A
10-BIT CHAR B
SO
[0:3]
±
TX[0]
TXLAT
TX[9]
TX
[0:3]
[0:4]
CHAR B[4:0]
CHAR B[9:5]
TC
Figure 4. Transmitter section latency. TX[0] is first on serial wire.
5