6
HDMP-1636A/1646A/T1636A (Receiver Section) – Gigabit Ethernet
Timing Characteristics
T
A
= 0°C to +70°C, V
CC
= 3.15 V to 3.45 V
Symbol
b_sync
[1,2]
f_lock
t
valid_before
t
valid_after
t
duty
t
A-B[3]
t_rxlat
[4]
Parameter
Bit Sync Time
Frequency Lock at Powerup
Time Data Valid Before Rising Edge of RBC
Time Data Valid After Rising Edge of RBC
RBC Duty Cycle
Rising Edge Time Difference between
RBC0 and RBC1
Receiver Latency
Units
bits
µs
nsec
nsec
%
nsec
nsec
bits
2.5
1.5
40
7.5
22.4
28.0
60
8.5
Min.
Typ.
Max.
2500
500
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C
PLL
= 0.1
µF.
3. Garranteed at room temperature.
4. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
HDMP-1636/1646A/T1636A (Receiver Section) – Fibre Channel
Timing Characteristics
T
A[1]
= 0°C to +70°C, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
b_sync
[2,3]
Bit Sync Time
t
valid_before
Time Data Valid Before Rising Edge of RBC
t
valid_after
Time Data Valid After Rising Edge of RBC
t
duty
RBC Duty Cycle
t
A-B[4]
Rising Edge Time Difference between
RBC0 and RBC1.
t_rxlat
[5]
Receiver Latency
Units
bits
nsec
nsec
%
nsec
nsec
bits
Min.
3
1.5
40
8.9
Typ.
Max.
2500
9.4
24.5
26
60
9.9
Notes:
1. Device tested and characterized under T
A
conditions specified, with T
C
monitored at approximately 20° higher than T
A
.
2. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
3. Tested using C
PLL
= 0.1
µF.
4. The RBC clock skew is calculated as t
A-B(max)
- t
A-B(min)
.
5. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
