5
HDMP-1636/1646A/T1636A (Transmitter Section) – Fibre Channel
Timing Characteristics
T
A[1]
= 0°C to +70°C, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
t
setup
Setup Time
t
hold
Hold Time
t_txlat
[2]
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
2
1.5
Typ.
Max.
4.2
4.4
Notes:
1. Device tested and characterized under T
A
conditions specified, with T
C
monitored at approximately 20° higher than T
A
.
2. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
REFCLK
1.4 V
2.0 V
TX[0]-TX[9]
DATA
DATA
DATA
DATA
DATA
0.8 V
t
SETUP
t
HOLD
Figure 3. Transmitter Section Timing.
DATA BYTE A
DATA BYTE B
± DOUT
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
t_TXLAT
TX[0]-TX[9]
DATA BYTE B
DATA BYTE C
REFCLK
1.4 V
Figure 4. Transmitter Latency.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
