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HDLG-2416 参数 Datasheet PDF下载

HDLG-2416图片预览
型号: HDLG-2416
PDF下载: 下载PDF文件 查看货源
内容描述: 四个字符5.0毫米( 0.2英寸)智能5× 7文数字显示 [Four Character 5.0 mm (0.2 inch) Smart 5 x 7 Alphanumeric Displays]
分类和应用: 显示器光电驱动
文件页数/大小: 12 页 / 340 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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10
strobing the blank input). All of
these blanking modes affect only
the output drivers, maintaining the
contents and write capability of
the internal RAMs and Control
Register, so that normal loading of
RAMs and Control Register can
take place even with the display
blanked.
Figure 3 shows how the Extended
Function Disable (bit D
6
of the
Control Register), Master Blank
(bit D
2
of the Control Register),
Digit Blank Disable (bit D
1
of the
Attribute RAM), and BL input can
be used to blank the display.
When the Extended Function
Disable is a logic 1, the display
can be blanked only with the BL
input. When the Extended
Function Disable is a logic 0, the
display can be blanked through
the BL input, the Master Blank,
and the Digit Blank Disable. The
entire display will be blanked if
either the BL input is logic 0 or
the Master Blank is logic 1,
providing all Digit Blank Disable
bits are logic 0. Those digits with
Digit Blank Disable bits a logic 1
will ignore both blank signals and
remain ON. The Digit Blank
Disable bits allow individual
characters to be blanked or
flashed in synchronization with the
BL input.
EFD
0
0
0
0
0
1
1
MB
0
0
X
1
1
X
X
DBD
n
0
X
1
0
1
X
X
BL
0
1
0
X
1
0
1
Display Blanked by BL
Display ON
Display Blanked by BL. Individual characters
"ON" based on "1" being stored in DBD
n
Display Blanked by MB
Display Blanked by MB. Individual characters
"ON" based on "1" being stored in DBD
n
Display Blanked by BL
Display ON
Figure 3. Display Blanking Truth Table
Dimming
Dimming of the display is con-
trolled through either the BL input
or the Control Register. A pulse
width modulated signal can be
applied to the BL input to dim the
display. A three bit word in the
Control Register generates an
internal pulse width modulated
signal to dim the display. The
internal dimming feature is
enabled only if the Extended
Function Disable is a logic 0.
Bits 3-5 in the Control Register
provide internal brightness
control. These bits are interpreted
as a three bit binary code, with
code (000) corresponding to the
maximum brightness and code
(111) to the minimum brightness.
In addition to varying the display
brightness, bits 3-5 also vary the
average value of I
DD
. I
DD
can be
specified at any brightness level as
shown in Table 1.
Table 1. Current Requirements at Different Brightness Levels
Symbol
I
DD
(#)
D
5
D
4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
D
3
0
1
0
1
0
1
0
1
Brightness
100%
60%
40%
27%
17%
10%
7%
3%
25
°
C Typ.
110
66
45
30
20
12
9
4
25
°
C Max.
130
79
53
37
24
15
11
6
Max. over Temp.
160
98
66
46
31
20
15
9
Units
mA
mA
mA
mA
mA
mA
mA
mA