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HCTL1100 参数 Datasheet PDF下载

HCTL1100图片预览
型号: HCTL1100
PDF下载: 下载PDF文件 查看货源
内容描述: 通用运动控制IC [General Purpose Motion Control ICs]
分类和应用:
文件页数/大小: 40 页 / 437 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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12
Pin Descriptions and Functions
Input/Output Pins
Pin Number
Symbol
AD0/DB0-
AD5/DB5
DB6, DB7
Input Signals
Pin Number
Symbol
CHA/CHB
PDIP PLCC
31, 30 34, 33
Description
Channel A, B – Input pins for position feedback from an incremental
shaft encoder. Two channels, A and B, 90 degrees out of phase are
required.
Index Pulse – Input from the reference or index pulse of an incre-
mental encoder. Used only in conjunction with the Commutator. Either
a low or high true signal can be used with the Index pin. See Timing
Diagrams and Encoder Interface section for more detail.
Read/Write – Determines direction of data exchange for the I/O port.
Address Latch Enable – Enables lower 6 bits of external data bus into
internal address latch.
Chip Select – Performs I/O operation dependent on status of R/W line.
For a Write, the external bus data is written into the internal
addressed location. For Read, data is read from an internal location
into an internal output latch.
Output Enable – Enables the data in the internal output latch onto the
external data bus to complete a Read operation.
Limit Switch – An internal flag which when externally set, triggers an
unconditional branch to the Initialization/Idle mode before the next
control sample is executed. Motor Command is set to zero. Status of
the Limit flag is monitored in the Status register.
Stop Flag – An internal flag that is externally set. When flag is set
during Integral Velocity Control mode, the Motor Command is
decelerated to a stop.
Reset – A hard reset of internal circuitry and a branch to Reset mode.
External Clock
Voltage Supply – Both V
DD
pins must be connected to a 5.0 volt supply.
Circuit Ground
Used to synchronize multiple HCTL-1100 sample timers.
Not connected. These pins should be left floating.
PDIP PLCC
2-7
8, 9
3-8
9, 10
Description
Address/Data Bus – Lower 6 bits of 8-bit I/O port which are
multiplexed between address and data.
Data bus – Upper 2 bits of 8-bit I/O port used for data only.
Index
33
36
R/W
ALE
CS
37
38
39
41
42
43
OE
Limit
40
14
44
15
Stop
15
16
Reset
ExtClk
V
DD
GND
SYNC
NC
36
34
40
37
11, 35 12, 38
10, 32 1, 11,
23, 35
1
2
17, 39