As shown in Figure 17, 0.1 µF
bypass capacitors (C1, C2)
should be located as close as
possible to the pins of the
HCPL-7510. The bypass
frequencies and interfering
with the input signal. The
input filter also performs an
important reliability function—it stray capacitive coupling
reduces transient spikes from between the input and the
ESD events flowing through the output circuits. To obtain
affect the isolation transient
immunity (CMTI) of the
HCPL-7510, due primarily to
capacitors are required
because of the high-speed
digital nature of the signals
inside the HCPL-7510. A 0.01
µF bypass capacitor (C2) is
also recommended at the
input due to the switched-
capacitor nature of the input
circuit. The input bypass
capacitor also forms part of
the anti-aliasing filter, which
is recommended to prevent
high frequency noise from
aliasing down to lower
current sensing resistor.
optimal CMTI performance, the
layout of the PC board should
minimize any stray coupling
by maintaining the maximum
possible distance between the
input and output sides of the
circuit and ensuring that any
ground or power plane on the
PC board does not pass
PC Board Layout
The design of the printed
circuit board (PCB) should
follow good layout practices,
such as keeping bypass
capacitors close to the supply
pins, keeping output signals
away from input signals, the
use of ground and power
planes, etc. In addition, the
layout of the PCB can also
directly below or extend much
wider than the body of the
HCPL-7510.
FLOATING
POSITIVE
SUPPLY
HV+
GATE DRIVE
CIRCUIT
U1
78L05
µC
IN OUT
+5 V
C2
0.1 µF
C1
0.1 µF
VDD1
VIN+
VIN-
VDD2
VOUT
VREF
1
2
3
8
R5
7
6
A/D
VREF
GND
68 Ω
C3
MOTOR
0.01 µF
C4
C5
C6
R1
+
-
4 GND1
GND2 5
RSENSE
HCPL-7510
C6 = 150 pF
C4 = C5 = 0.1 µF
HV-
Figure 17. Recommended HCPL-7510 application circuit.
12
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
