Switching Specifications
Guaranteed across recommended operating conditions. Test conditions represent worst case values for the
parameter under test. Test conditions that are not specified can be anywhere within their operating range. All
typicals are at 25°C and 5 V supplies unless otherwise noted.
Parameter
Propagation
Delay Time
to Logic
Low Output
Symbol
t
PHL
Device
HCPL-7100
HCPL-7101
HCPL-7100
HCPL-7101
Propagation
Delay Time
to Logic
High Output
t
PLH
HCPL-7100
HCPL-7101
HCPL-7100
HCPL-7101
Pulse Width
Distortion
|t
PHL
- t
PLH
|
PWD
HCPL-7100
HCPL-7101
HCPL-7100
HCPL-7101
Data Rate
HCPL-7100
HCPL-7101
Propagation
Delay Skew
Output Rise
Time
(10-90%)
Output Fall
Time
(90-10%)
Random Jitter
t
PSK
t
R
HCPL-7101
HCPL-7100
HCPL-7101
t
F
HCPL-7100
HCPL-7101
RJ
HCPL-7101
12
10
8
7
50
ps rms
V
1
= 0-5 V square wave,
f = 25 MHz, input rise/
fall time = 5 ns.
R
L
= 10 kΩ,
C
L
= 5 pF.
TTL Threshold Levels.
C
L
= 50 pF
CMOS Signal Levels
C
L
= 15 pF
TTL Signal Levels
C
L
= 50 pF
CMOS Signal Levels
C
L
= 15 pF
TTL Signal Levels
12
6
12
6
ns
C
L
= 50 pF
CMOS Signal Levels
7
15
50
65
10
ns
ns
C
L
= 50 pF
CMOS Signal Levels
10
7
9
2
27
28
Min.
Typ.
Max.
70
40
70
40
70
40
70
40
20
6
20
6
MBd
% PWD < 30%
8
ns
C
L
= 15 pF
TTL Signal Levels
ns
C
L
= 50 pF
CMOS Signal Levels
7, 9
6, 7
ns
C
L
= 15 pF
TTL Signal Levels
ns
C
L
= 50 pF
CMOS Signal Levels
7, 8
5, 6
ns
C
L
= 15 pF
TTL Signal Levels
Unit
ns
Test Conditions
C
L
= 50 pF
CMOS Signal Levels
Fig.
7, 8
Note
5, 6
Propagation
Delay Time From
Output Enabled
to Logic High
Output
Propagation
Delay Time From
Output Enabled
to Logic Low
Output
t
PZH
13
12
ns
ns
ns
ns
t
PZL
11
10
1-408
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
