Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified.
Parameter
Propagation Delay Time to
High Output Level
Propagation Delay Time to
Low Output Level
Propagation Delay
Difference Between Any
Two Parts or Channels
Rise Time
Fall Time
Output High Level Common
Mode Transient Immunity
Output Low Level Common
Mode Transient Immunity
Symbol
t
PLH
t
PHL
PDD
Min.
0.1
0.1
-0.5
Typ.
0.2
0.3
Max.
0.7
0.7
0.5
Units
µs
µs
µs
Test
Conditions
Rg = 47
Ω,
Cg = 3 nF,
f = 10 kHz,
Duty Cycle =
50%,
I
F =
8 mA,
V
CC
= 30 V
Fig.
10,11,
12,13,
14,17
Note
14
10
t
R
t
F
|CM
H
|
|CM
L
|
10
10
50
50
ns
ns
kV/µs
kV/µs
T
A
= 25°C,
V
CM
= 1 kV
18
18
11
12
Package Characteristics
Parameter
Input-Output Momentary
Withstand Voltage
Input-Output Resistance
Input-Output Capacitance
Symbol
V
ISO
R
I-O
C
I-O
Min.
2500
Typ.
Max.
Units
V
rms
Ω
pF
Test
Conditions
T
A
=25°C,
RH<50% for
V
I-O
=500 V
Freq=1 MHz
Fig.
Note
8,9
9
10
12
0.6
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10
µs,
maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I
O
peak
minimum = 0.4 A. See Application section for additional details on limiting I
OL
peak.
3. Derate linearly above 85°C, free air temperature at the rate of 4.0 mW/°C.
4. Input power dissipation does not require derating.
5. Maximum pulse width = 50
µs,
maximum duty cycle = 0.5%.
6. In this test, V
OH
is measured with a DC load current. When driving capacitive load V
OH
will approach V
CC
as I
OH
approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
≥
3000 V
rms
for 1 second (leakage detection
current limit I
I-O
≤
5
µA).
This test is performed before 100% production test for partial discharge (method B) shown in the VDE 0884 Insulation
Characteristics Table, if applicable.
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. PDD is the difference between t
PHL
and t
PLH
between any two parts or channels under the same test conditions.
11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse V
CM
to assure that the output
will remain in the high state (i.e. Vo > 6.0 V).
12. Common mode transient immunity in a low state is the maximum tolerable |dV
CM
/dt| of the common mode pulse, V
CM
, to assure that the output
will remain in a low state (i.e. Vo < 1.0 V).
13. This load condition approximates the gate load of a 1200 V/25 A IGBT.
14. The power supply current increases when operating frequency and Qg of the driven IGBT increases.
7
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