Applications Information
Power Consumption
The HCPL-90xx and HCPL-09xx
CMOS digital isolators achieves
low power consumption from the
manner by which they transmit
data across isolation barrier. By
detecting the edge transitions of
the input logic signal and con-
verting this to a narrow current
pulse, which drives the isolation
barrier, the isolator then latches
the input logic state in the output
latch. Since the current pulses
are narrow, about 2.5 ns wide, the
power consumption is indepen-
dent of mark-to-space ratio and
solely dependent on frequency.
The approximate power supply
current per channel is:
I(Input) = 40(f/fmax)(1/4) mA
where f = operating frequency,
fmax = 50 MHz.
Signal Status on Start-up and
Shut Down
To minimize power dissipation,
the input signals to the channels
of HCPL-90xx and HCPL-09xx
digital isolators are differenti-
ated and then latched on the
output side of the isolation
barrier to reconstruct the signal.
This could result in an ambigu-
ous output state depending on
power up, shutdown and power
loss sequencing. Therefore, the
designer should consider the
inclusion of an initialization
signal in this start-up circuit.
Bypassing and PC Board Layout
The HCPL-90xx and HCPL-09xx
digital isolators are extremely
easy to use. No external interface
circuitry is required because the
isolators use high-speed CMOS IC
technology allowing CMOS logic
to be connected directly to the
inputs and outputs. As shown in
Figure 1, the only external
components required for proper
operation are two 47 nF ceramic
capacitors for decoupling the
power supplies. For each capaci-
tor, the total lead length between
both ends of the capacitor and the
power-supply pins should not
exceed 20 mm. Figure 2 illustrates
the recommended printed circuit
board layout for the HCPL-9000
or HCPL-0900. For data rates in
excess of 10MBd, use of ground
planes for both GND
1
and GND
2
is
highly recommended.
V
DD1
C1
IN
1
1
HCPL-9000
or
HCPL-0900
8
C2
7
6
5
GND
2
V
OE
V
DD2
2
NC 3
GND
1
4
OUT
1
Note:
C1, C2 = 47 nF ceramic capacitors
Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900.
V
DD1
HCPL-9000
or
HCPL-0900
V
DD2
V
OE
C2
OUT
1
GND
2
IN
1
C1
GND
1
Figure 2. Recommended Printed Circuit Board Layout.
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