Pin Description, Digital Interface IC
Symbol
Description
CCLK Clock input for the Serial Configuration
Interface (SCI). Serial Configuration
data is clocked in on the rising edge
of CCLK.
CLAT Latch input for the Serial Configuration
Interface (SCI). The last 8 data bits
clocked in on CDAT by CCLK are
latched into the appropriate
configuration register on the rising
edge of CLAT.
CDAT Data input for the Serial Configuration
Interface (SCI). Serial configuration
data is clocked in MSB first.
MCLK1 Channel 1 Isolated Modulator clock
input. Input Data on MDAT1 is clocked
in on the rising edge of MCLK1.
Symbol
Description
V
DD
Supply voltage (4.5 V to 5.5 V).
CHAN
Channel select input. The input level on
CHAN determines which channel of
data is used during the next conversion
cycle. An input low selects channel 1,
a high selects channel 2.
Serial clock input. Serial data is clocked
out of SDAT on the falling edge of SCLK.
Serial data output. SDAT changes from
high impedance to a logic low output
at the start of a conversion cycle.
SDAT then goes high to indicate that
data is ready to be clocked out. SDAT
returns to a high-impedance state after
all data has been clocked out and CS
has been brought high.
Conversion start input. Conversion
begins on the falling edge of CS. CS
should remain low during the entire
conversion cycle and then be brought
high to conclude the cycle.
Continuous, programmable-threshold
detection for channel 1 input data. A
high level output on THR1 indicates
that the magnitude of the channel 1
input signal is beyond a user
programmable threshold level between
160 mV and 310 mV. This signal
continuously monitors channel 1
independent of the channel select
(CHAN) signal.
High speed continuous over-range
detection for channel 1 input data. A
high level output on OVR1 indicates
that the magnitude of the channel 1
input is beyond full-scale. This signal
continuously monitors channel 1
independent of the CHAN signal.
Master reset input. A logic high input
for at least 100 ns asynchronously
resets all configuration registers to
their default values and zeroes the
Offset Calibration registers.
SCLK
SDAT
MDAT1
Channel 1 Isolated Modulator data
input.
CS
MCLK2
Channel 2 Isolated Modulator clock
input. Input Data on MDAT2 is clocked
in on the rising edge of MCLK2.
THR1
MDAT2
Channel 2 Isolated Modulator data
input.
OVR1
GND
Digital ground.
RESET
1-263
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