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HCPL-0721 参数 Datasheet PDF下载

HCPL-0721图片预览
型号: HCPL-0721
PDF下载: 下载PDF文件 查看货源
内容描述: 40 ns的传播延迟CMOS光电耦合器 [40 ns Propagation Delay CMOS Optocoupler]
分类和应用: 光电输出元件
文件页数/大小: 18 页 / 438 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Application Information
Bypassing and PC Board Layout
The HCPL-772X/072X
optocouplers are extremely easy
to use. No external interface
circuitry is required because the
HCPL-772X/072X use high-speed
CMOS IC technology allowing
CMOS logic to be connected
directly to the inputs and outputs.
As shown in Figure 10, the only
external components required for
proper operation are two bypass
capacitors. Capacitor values
should be between 0.01
µF
and
0.1
µF.
For each capacitor, the
total lead length between both
ends of the capacitor and the
power-supply pins should not
exceed 20 mm. Figure 11
illustrates the recommended
printed circuit board layout for
the HPCL-772X/072X.
V
DD1
C1
V
I
1
2
NC 3
GND
1
4
8
C2
7 NC
6
5
GND
2
72X
YWW
V
DD2
V
O
C1, C2 = 0.01 µF TO 0.1 µF
Figure 10. Recommended printed circuit board layout.
V
DD1
V
I
C1
V
DD2
72X
YWW
C2
V
O
GND
1
GND
2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 11. Recommended printed circuit board layout.
Propagation Delay, Pulse-Width
Distortion and Propagation Delay Skew
Propagation Delay is a figure of
merit which describes how quickly
a logic signal propagates through a
system. The propagation delay
from low to high (t
PLH
) is the
amount of time required for an
input signal to propagate to the
output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (t
PHL
) is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low. See
Figure 12.
INPUT
V
I
t
PLH
OUTPUT
V
O
90%
10%
t
PHL
90%
5 V CMOS
50%
0V
10%
V
OH
2.5 V CMOS
V
OL
Figure 12.
10