ATF-55143 Applications
Information
Introduction
Agilent Technologies’s ATF-55143
is a low noise enhancement mode
PHEMT designed for use in low
cost commercial applications in
the VHF through 6 GHz frequency
range. As opposed to a typical
depletion mode PHEMT where the
gate must be made negative with
respect to the source for proper
operation, an enhancement mode
PHEMT requires that the gate be
made more positive than the
source for normal operation.
Therefore a negative power
supply voltage is not required for
an enhancement mode device.
Biasing an enhancement mode
PHEMT is much like biasing the
typical bipolar junction transistor.
Instead of a 0.7V base to emitter
voltage, the ATF-55143 enhance-
ment mode PHEMT requires
about a 0.47V potential between
the gate and source for a nominal
drain current of 10 mA.
Matching Networks
The techniques for im pedance
matching an enhancement mode
device are very similar to those
for matching a depletion mode
device. The only difference is in
the method of supplying gate
bias. S and Noise Parameters for
various bias conditions are listed
in this data sheet. The circuit
shown in Figure 1 shows a typical
LNA circuit normally used for
900 and 1900 MHz applications
(Consult the Agilent Technologies
website for application notes
covering specific applications).
High pass impedance matching
networks consisting of L1/C1 and
L4/C4 pr ovide the appropriate
match for noise figure, gain, S11
and S22. The high pass structure
also provides low frequency gain
reduction which can be beneficial
from the standpoint of improving
out-of-band rejection.
INPUT
Zo
C1
Q1
L1
L2
R4
C2
L3
C5
R3
R5
R1
C3
R2
C6
C4
Zo
OUTPUT
L4
Vdd
Figure 1. Typical ATF-55143 LNA with Passive
Biasing.
Capacitors C2 and C5 pr ovide a
low impedance in-band RF
bypass for the matching net-
works. Resistors R3 and R4
provide a very important low
frequency termination for the
device. The resistive termination
improves low frequency stability.
Capacitors C3 and C6 provide
the low frequency RF bypass for
resistors R3 and R4. Their value
should be chosen carefully as C3
and C6 also provide a termina-
tion for low frequency mixing
products. These mixing products
are as a result of two or more in-
band signals mixing and produc-
ing third order in-band distortion
products. The low frequency or
difference mixing products are
terminated by C3 and C6. For
best suppression of third order
distortion products based on the
CDMA 1.25 MHz signal spacing,
C3 and C6 should be 0.1
µF
in
value. Smaller values of capaci-
tance will not suppress the
generation of the 1.25 MHz
difference signal and as a result
will show up as poorer two tone
IP3 results.
Bias Networks
One of the major advantages of
the enhancement mode technol-
ogy is that it allows the designer
to be able to dc ground the
source leads and then merely
apply a positive voltage on the
gate to set the desired amount of
quiescent drain cur rent I
d
.
Whereas a depletion mode
PHEMT pulls maximum drain
current when V
gs
= 0V, an en-
hancement mode PHEMT pulls
only a small amount of leakage
current when V
gs
=0 V. Only when
V
gs
is increased above V
th
, the
device threshold voltage, will
drain cur rent star t to flow. At a
V
ds
of 2.7V and a nominal V
gs
of
0.47V, the drain cur rent I
d
will be
approximately 10 mA. The data
sheet suggests a minimum and
maximum V
gs
over which the
desired amount of drain current
will be achieved. It is also impor-
tant to note that if the gate
terminal is lef t open circuited,
the device will pull some amount
of drain current due to leakage
current creating a voltage differ-
ential between the gate and
source terminals.
Passive Biasing
Passive biasing of the ATF-55143
is accomplished by the use of a
voltage divider consisting of R1
and R2. The voltage for the
divider is deriv ed from the drain
voltage which provides a form of
voltage feedback through the use
of R3 to help keep drain current
constant. Resistor R5 (approxi-
mately 10 kΩ) is added to limit
the gate current of enhancement
mode devices such as the
ATF-55143. This is especially
important when the device is
driven to P
1dB
or P
SAT
.
Resistor R3 is calculated based
on desired V
ds
, I
ds
and available
power supply voltage.
R3 =
V
DD
– V
ds
I
ds
+ I
BB
p
(1)
V
DD
is the power supply voltage.
V
ds
is the device drain to source
voltage.
I
ds
is the desired drain current.
I
BB
is the current flowing through
the R1/R2 resistor voltage
divider network.
14
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