1 x 10
-2
1 x 10
-3
BIT ERROR RATE
1 x 10
-4
1 x 10
-5
1 x 10
-6
1 x 10
-7
1 x 10
-8
1 x 10
-9
1 x 10
-10
1 x 10
-11
1 x 10
-12
-6
AFBR-5803 SERIES
without violating the Annex E
allocation example. In practice
the typical contribution of the
Agilent transceivers is well
below these maximum allowed
amounts.
Recommended Handling Precautions
Agilent recommends that
normal static precautions be
taken in the handling and
assembly of these transceivers
to prevent damage which may
be induced by electrostatic
discharge (ESD). The AFBR-
5800 series of transceivers
meet MIL-STD-883C Method
3015.4 Class 2 products.
Care should be used to avoid
shorting the receiver data or
signal detect outputs directly
to ground without proper
current limiting impedance.
CENTER OF SYMBOL
-4
-2
0
2
4
RELATIVE INPUT OPTICAL POWER - dB
CONDITIONS:
1. 155 MBd
2. PRBS 2
7
-1
3. CENTER OF SYMBOL SAMPLING
4. T
A
= +25˚C
5. V
CC
= 3.3 V to 5 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Rx
Tx
Figure 6. Bit Error Rate vs. Relative Receiver
Input Optical Power.
;;
;;
NO INTERNAL CONNECTION
AFBR-5803Z
TOP VIEW
;;
;;
NO INTERNAL CONNECTION
Transceiver Jitter Performance
The Agilent 1300 nm
transceivers are designed to
operate per the system jitter
allocations stated in Tables E1
of Annexes E of the FDDI
PMD and LCF-PMD standards.
The Agilent 1300 nm
transmitters will tolerate the
worst case input electrical
jitter allowed in these tables
without violating the worst
case output jitter requirements
of Sections 8.1 Active Output
Interface of the FDDI PMD and
LCF-PMD standards.
The Agilent 1300 nm receivers
will tolerate the worst case
input optical jitter allowed in
Sections 8.2 Active Input
Interface of the FDDI PMD and
LCF-PMD standards without
violating the worst case output
electrical jitter allowed in the
Tables E1 of the Annexes E.
The jitter specifications stated
in the following 1300 nm
transceiver specification tables
are derived from the values in
Tables E1 of Annexes E. They
represent the worst case jitter
contribution that the trans-
ceivers are allowed to make to
the overall system jitter
6
;; ;; ;;; ;; ;; ;; ;; ;;; ;;
;; ;; ;;; ;; ;; ;; ;; ;;; ;;
C1
C2
V
CC
TERMINATION
AT PHY
DEVICE
INPUTS
L1
V
CC
R5
R7
C6
R6
R8
L2
R2
R1
C5
TERMINATION
AT TRANSCEIVER
INPUTS
R3
R4
Rx
V
EE
1
RD
2
RD
3
SD
4
Rx
V
CC
5
Tx
V
CC
6
TD
7
TD
8
Tx
V
EE
9
C3
C4
V
CC
FILTER
AT V
CC
PINS
TRANSCEIVER
R9
R10
;; ;;
;; ;;
RD
RD
;;
;;
SD
;;;
;;;
V
CC
;;;
;;;
TD
;;
;;
TD
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS FOR +5.0 V OPERATION, 82 OHMS FOR +3.3 V OPERATION.
R2 = R3 = R5 = R7 = R9 = 82 OHMS FOR +5.0 V OPERATION, 130 OHMS FOR +3.3 V OPERATION.
C1 = C2 = C3 = C5 = C6 = 0.1 µF.
C4 = 10 µF.
L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.
Figure 7. Recommended Decoupling and Termination Circuits
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
