3
Functional Diagrams
16 Pin DIP
Through Hole
2 Channels
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
2 Channels
16 Pin Flat Pack
Unformed Leads
4 Channels
20 Pad LCCC
Surface Mount
2 Channels
15
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
V
CC2
V
1
2
3
4
8
7
6
5
1
V
8
CC
CC
V
V
CC
15
14
13
CC
19
20
13
12
V
O2
V
O1
O2
V
V
V
V
V
E
O1
O2
O3
O1
2
3
4
7
6
5
GND
2
V
V
OUT
V
CC1
2
3
10
V
O1
V
O2 12
11
V
O4
GND
GND
1
GND
GND
GND
10
9
7
8
Note: All DIP and flat pack devices have common VCC and ground. Single channel DIP has an enable pin 7. LCCC (leadless ceramic
chip carrier) package has isolated channels with separate VCC and ground connections. All diagrams are “top view.”
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
0.20 (0.008)
0.33 (0.013)
MIN.
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Leaded Device Marking
Leadless Device Marking
Agilent DESIGNATOR
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
Agilent DESIGNATOR
Agilent P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
• XXXX
XXXXXX
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Agilent CAGE CODE*
Agilent P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
COUNTRY OF MFR.
Agilent CAGE CODE*
•
50434
XXX 50434
ESD IDENT
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY