Table 1-1. Signal source assignment
Pin No. Signal name
Signal standard
1
GND
0 ꢀ
2
3
4
5
6
7
8
9
INPUT1
OUTPUT1
OUTPUT2
TTL level, pulse input (pulse width: 1 µs or above)
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, latch output
TTL level, input mode: LOW, output mode: HIGH
TTL level, input mode: LOW, output mode: HIGH
OUTPUT PORT A0
OUTPUT PORT A1
OUTPUT PORT A2
OUTPUT PORT A3
OUTPUT PORT A4
OUTPUT PORT A5
OUTPUT PORT A6
OUTPUT PORT A7
OUTPUT PORT B0
OUTPUT PORT B1
OUTPUT PORT B2
OUTPUT PORT B3
OUTPUT PORT B4
OUTPUT PORT B5
OUTPUT PORT B6
OUTPUT PORT B7
I/O PORT C0
I/O PORT C1
I/O PORT C2
I/O PORT C3
I/O PORT D0
I/O PORT D1
I/O PORT D2
I/O PORT D3
PORT C STATUS
PORT D STATUS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
WRITE STROBE SIGNAL TTL level, active low, pulse output
(width: 10 µs; typical)
+5 ꢀ PULLUP
32
33
SWEEP END SIGNAL
TTL level, active low, pulse output
(width: 20 µs; typical)
34
35
36
+5 ꢀ
+5 ꢀ, 100 mA MAX
TTL level, PASS: HIGH, FAIL: LOW, latch output
PASS/FAIL SIGNAL
PASS/FAIL WRITE STROBE SIGNAL
TTL level, active low, pulse output
(width: 10 µs; typical)
17
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