3. I channel offset: A small dc
offset to cancel in-phase car-
rier leakage paths to the out-
put.
should be placed on the PCB as
close as possible to the TC932
package, and no more than 5
mm away.
Applications
The TC932 adds accurate vector
modulation to broadband signal
sources.
4. Q channel offset: A small dc
offset to cancel quadrature
carrier leakage paths to the
output.
Note that the TC932 output is
close to a square wave, contain-
ing strong harmonic content at
odd multiples of the LO frequen-
cy. External filtration is re-
quired if these harmonics are
unacceptable.
Biasing and Operation
Overview
TC932 operation requires a sin-
gle –6V power supply (“V ”),
and other biases and adjust-
ments as shown in Figure 1.
Two 50 uA current sources bias
internal detector diodes. A neg-
ative feedback loop automatical-
ly sets coarse quadrature and
stabilizes gain ratio and quadra-
ture against time and tempera-
Values for the above four should
be determined during calibra-
tion.
ss
Package
TC732’s 50 dB gain LO amplifi-
ers reduce drive requirement to
+8 dBm for low LO leakage,
while maintaining large, fast-
edged squarewaves at the mix-
ers’ LO ports. An output balun’s
common-mode rejection further
improves LO feedthru.
The TC932 is also avaiable in a
14-lead “Fastpak II” surface
mount package.
Baseband ports
The baseband I and Q inputs
connect directly to the sources
of the passive bridge mixer
FETs. There are also on-chip
50ohm resistors to ground on
each port. Port input impedance
changes slightly as a function of
ture. V optimizes mixer
blo
linearity. There are also four ad-
justments which are frequency
dependent:
An output balun provides up to
6 dB more output signal power
with only about 3 dB more noise
output power (since the noise is
mostly uncorrelated).
1. V –V : Fine adjustment of
ci cq
quadrature.
2. I (or Q) Gain: To compensate
for slight channel conversion
efficiency differences.
V
and frequency. Input im-
blo
pedance is mostly 50 ohms and
A V bypass capacitor of 0.1 uF
ss
Vin
I
V
BLO
-
+
0.1 uF
50 uA
-
I
+
I
Gain Adjust
Offset
15
19
14
13
18
Package boundary
Chip boundary
27pF
27pF
BLO
V
D
i
Ibar
I
V
ci
4.5k
400
50
4k
V -V
3k
50
ci cq
+
_
Out
9
8
4k
RF
out
Av>400
+
_
3k
3k
LO
in
Outbar
Vc
20
50
4k
4k
3k
1,5,6,11,12,16,17,22
50
50
Qbar
27pF
4.5k
Q
D
V
Vss
q
cq
27pF
1200 pF
4
2
3
21
7,10
0.1 uF
+
Q
--
Q
+
50 uA
V
=-6V
ss
-
Gain Adjust
Offset
Vin
Q
Figure 1.
TC932 Electrical Control Diagram
TC932 rev.1.03
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
