T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
26 Register Set Summary
The following section contains tables that list a summary of the entire register set for the T9000.
Table 126. Register Set Summary Global Registers
Reg
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00, Global Interrupt Register 0
GIR0
R
—
—
—
—
—
—
XI0I
0
125I
0
UII
0
SII
0
GPIOI
0
RESET Default
0x01, Global Interrupt Register 1
GIR1
R
—
0
—
0
—
0
XI1I
0
HDLCI
0
GCII
0
CMPI
0
PWMI
0
RESET Default
0x02, Global Interrupt Enable Register
GIE
R/W
—
0
—
0
—
0
125IE
0
II1E
0
XI1E
0
II0E
0
XI0E
0
RESET Default
0x03, Microcontroller Clock Control Register
UPCK
R/W
CLKOE
1
—
0
—
0
—
0
—
0
UPCK2
1
UPCK1
1
UPCK0
1
RESET Default
0x04, Watchdog Timer
WDT
R/W
WDTE
0
WDT6
1
WDT5
1
WDT4
1
WDT3
1
WDT2
1
WDT1
1
WDT0
1
RESET Default
Table 127. Register Set Summary DFAC Registers
0x05, DFAC Configuration Register
DFCF
R/W
ILOSS
USIMRST
URESET
—
UOADS
ACT_ANSI AUTOEOC GRESET
RESET Default
0
0
0
0
1
0
1
0
0x06, Data Flow Register
DFR
R/W
U_FORCE_B2UP U_FORCE_B1UP FORCE_D
PFS2_ACT PFS1_ACT
B2_SEL
0
B1_SEL
0
BSWAP
0
RESET Default
0
0
0
0
0
Table 128. Register Set Summary U-Interface Control Registers
0x07, U-Interface Control Register #0
UCR0
R/W
NTM_n
1
PS1
1
PS2
1
SAI
0
XPCY
0
F_ACTUP ACTUP
ISTP
0
RESET Default
0
0
0x08, U-Interface Control Register #1
UCR1
R/W
R64T
1
R25T
1
R16T
1
R15T
1
ULBKMUX
0
ULLBK
0
USPMAG USSP_E
RESET Default
0
0
0x09, U-Interface Status Register #0
USR0
R
AIB_n
1
FEBE_n NEBE_n
UOA_n
1
DEA_n
1
OOF_n
0
XACT
0
ACTDN
0
RESET Default
1
1
0x0A, U-Interface Status Register #1
USR1
R
—
—
R64R
1
R54R
1
R44R
1
R34R
1
R25R
1
R16R
1
R15R
1
RESET Default
118
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
