T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
12 PWM Module (continued)
12.6 PWM Module Register Set (continued)
Table 108. PW1VH: Pulse-Width Modulator 1 Pulse-Width Value, High Byte (0x48)
Reg
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PW1VH
R/W
PW1VH7 PW1VH6 PW1VH5 PW1VH4 PW1VH3 PW1VH2 PW1VH1 PW1VH0
RESET Default
—
—
—
—
—
—
—
—
Bit #
Symbol
Name/Description
7—0 PW1VH[7:0] PWM 1 Pulse-Width Value, High Byte. When manual pulse-width control is pro-
grammed, the pulse-width high can be expressed as follows:
PW1 = PW1VH[7:0] * tick when PW1R.[1:0] = 11.
PW1 = PW1VH[7:1] * tick when PW1R.[1:0] = 10.
PW1 = PW1VH[7:2] * tick when PW1R.[1:0] = 01.
PW1 = PW1VH[7:3] * tick when PW1R.[1:0] = 00.
If auto mode is selected, it contains the high-order byte of the programmed sine fre-
quency (Fs).
Table 109. PW1VL: Pulse-Width Modulator 1 Pulse-Width Value, Low Byte (0x49)
Reg
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PW1VL
R/W
PW1VL7 PW1VL6 PW1VL5 PW1VL4 PW1VL3 PW1VL2 PW1VL1 PW1VL0
RESET Default
—
—
—
—
—
—
—
—
Bit #
Symbol
Name/Description
PWM#1 Pulse-Width Value, Low Byte. Its function depends on the operation mode
selected.
7—0
PW1VL[7:0]
When auto operation mode is selected (PW1CF[PW1AUTO] = 1), it contains the low-
order byte of the programmed sine frequency (Fs).
When manual/timer operation mode is selected (PW1CF[PW1AUTO] = 0), it defines the
rate at which PWIR[PW1I] interrupt register bit will be asserted:
PWIR[PW1I] assertion rate = PP1 x (PW1VL + 1).
Table 110. PWIR: Pulse-Width Modulator Interrupt Register (0x4A)
Reg
R/W
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
—
Bit 2
—
Bit 1
PW1I
0
Bit 0
PW0I
0
PWIR
R
RESET Default
—
—
—
—
—
—
Note: All bits in this register are set to 1 upon occurrence of the corresponding interrupt condition, and are cleared
to 0 when the register is read.
Bit #
Symbol
Name/Description
7—2
—
Reserved.
PWM x Interrupt. This interrupt occurs only in manual/timer mode (PWxAUTO = 0).
Once the current PWV value initiates the PWM output waveform, this interrupt is
asserted to indicate to the microcontroller that it should load a new value within
PPx * (PWxVL + 1) ns. If the microcontroller does not load a new value within this win-
dow, the previously loaded value will be used to generate the new pulse. PWxCF[PWxIE]
is the enable bit for this interrupt.
1—0
PWxI
Lucent Technologies Inc.
103
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