T7507 Quad PCM Codec with Filters,
Termination Impedance, and Hybrid Balance
Data Sheet
August 1999
Functional Description (continued)
PCM Interface (continued)
T7507
C1 ≥ 0.07 µF
TO
VFXIN
CODEC
SLIC
26 dB
FILTERS
The entire device is placed in a powerdown mode if
FSEP remains low for 500 µs. Powerdown is not guar-
anteed if MCLK is lost unless the device is already in
the powerdown mode due to FSEP low for at least
500 µs.
R ≥ 100 kΩ
VCM = 2.4 V
The T7507 also offers an output pin, DxEN. This pin is
an open-drain output that pulses low during the period
when the DX output is enabled.
5-4821(F)
Figure 3. Typical Analog Input Section
Analog Interface
Microprocessor Serial Data Control and
The analog input section (Figure 3) includes an on-chip
buffer op amp and internal gain. Feedback paths (ZT
and HYBAL in Figure 1) are included in the T7507 to
generate signals needed for termination impedance
and hybrid balance.
L8567 SLIC/L7583 Switch (or EMR) Control
Interfaces
The basic logic control scheme is a serial data interface
between the microcontroller and the T7507. Through
this interface, an 8-bit input control word and an 8-bit
output status word is passed between the T7507 and
microcontroller. The input control word contains infor-
mation for the T7507, L8567 SLIC, and L7583 switch.
The output status word contains off-hook and thermal
shutdown status information from the L8567 SLIC and
L7583 switch. See the Input Word Definition and Out-
put Word Definition sections of this data sheet for spe-
cific details on the input and output words.
When matched with a SLIC with a transconductance
from tip/ring of 39.75 V/A and a differential gain to
tip/ring of 2 (such as the Lucent Technologies L8567),
and when a solid-state switch (such as the Lucent
L7583) and 50 Ω of series protection are used, the
T7507 will synthesize a complex line termination
impedance and hybrid balance network of 200 Ω +
680 Ω || 100 nF. Additionally, the T7507 will fix the
line circuit tip/ring to PCM transmit gain at 0 dB (at
1000 Hz, –0.7 dB, +0.3 dB) and will allow a user-select-
able (via the serial control input) PCM to tip/ring receive
gain of –3.5 dB or –7.0 dB (at 1000 Hz, –0.7 dB,
+0.3 dB). Thus, the ac interface between the T7507
and the L8567 SLIC consists of a single dc blocking
capacitor in the transmit direction, and a direct connec-
tion requiring no external components in the receive
direction. The T7507/L8567/L7583 chip set is designed
to meet all MPT requirements for the People’s Republic
of China.
Control and status information are passed between the
T7507 and L8567 SLIC/L7583 switch via a latched par-
allel data interface. Data latches are integrated into the
L8567 SLIC inputs and outputs and L7583 switch
inputs. Thus, a given data I/O on the T7507 serves the
corresponding data I/O on the L8567 SLIC for the four
channels associated with the quad T7507. Additionally,
a given data output on the T7507 serves the corre-
sponding data inputs on the L7583 switch for the four
channels associated with the quad T7507. Status infor-
mation from the L7583 switch is passed to the T7507
on a per-line basis.
Transmission Levels
The T7507 control interface consists of an 8-bit input
serial shift register, an 8-bit output serial shift register,
an 8-bit loop status input latch, logic to generate the
enable (EN) pulses required to control the SLIC and
switch data latches, interface logic/buffers between the
DI shift register and the internal codec control, and
interface logic buffers between the SLIC/switch output
control leads.
Zero transmission-level points are specified relative to
the digital milliwatt sequence prescribed by ITU-T rec-
ommendation G.711. Under these conditions, an ana-
log input of 0.0452 Vrms applied to VFXIN produces a
0 dBm digital code, while a 0 dBm code input at DR
produces an output of 0.394 Vrms differentially at
VFRON/VFROP when using the –7.0 dB gain mode
(data bit D4 = 0).
8
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
