Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
hxH[9:0]
hx1[9:0]
hCLK
10
10
10
10
10
10
10
10
10
PFU
2
PFU
2
PFU
2
2
2
2
2
2
2
2
2
2
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
hx1[9:0]
hx5[9:0]
hxL[9:0]
10
10
10
hxH[9:0]
hx1[9:0]
hCLK
PFU
2
PFU
2
PFU
2
hx1[9:0]
hx5[9:0]
hxL[9:0]
10
10
10
hxH[9:0]
hx1[9:0]
hCLK
PFU
2
PFU
2
PFU
2
hx1[9:0]
hx5[9:0]
hxL[9:0]
10
10
10
KEY: CONFIGURABLE SIGNAL-LINE BREAKS:
LINE-BY-LINE
2
2 OF 10
10
PLC BOUNDARY
5-5767(F)
Figure 20. Multiple PLC View of Inter-PLC Routing
32
Lucent Technologies Inc.