Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 54. OR3Cxx ExpressCLK to Output Delay (Pin-to-Pin)
<
<
<
<
<
DD
A
DD
A
L
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
T
+85 °C; C = 50 pF.
<
<
<
DD
A
A
T
L =
OR3Txxx Commercial: V
50 pF.
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
+85 °C;C
Speed
Description
Device
Unit
-4
-5
-6
-7
J
DD
(T = 85 °C, V = min)
Min
Max
Min
Max
Min
Max
Min
Max
→
ECLK Middle Input Pin OUTPUT Pin
(Fast)
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
9.93
10.10
—
—
—
—
—
—
7.78
7.84
7.96
8.08
8.28
—
—
—
—
—
5.40
5.43
5.48
5.54
5.64
—
—
—
—
—
4.38
4.40
4.44
4.49
4.58
ns
ns
ns
ns
ns
→
ECLK Middle Input Pin OUTPUT Pin
(Slewlim)
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
12.37
12.54
—
—
—
—
—
—
9.77
9.83
9.95
10.07
10.27
—
—
—
—
—
6.07
6.10
6.15
6.21
6.31
—
—
—
—
—
4.91
4.93
4.97
5.02
5.11
ns
ns
ns
ns
ns
→
ECLK Middle Input Pin OUTPUT Pin
(Sinklim)
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
13.73
13.90
—
—
—
—
—
—
11.12
11.18
11.30
11.42
11.62
—
—
—
—
—
10.92
10.95
11.00
11.06
11.16
—
—
—
—
—
9.65
9.67
9.71
9.76
9.85
ns
ns
ns
ns
ns
Additional Delay if ECLK Corner Pin Used
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
1.97
1.97
—
—
—
—
—
—
1.91
1.91
1.91
1.91
1.90
—
—
—
—
—
1.80
1.90
2.09
2.28
2.57
—
—
—
—
—
1.58
1.67
1.84
2.02
2.29
ns
ns
ns
ns
ns
Notes:
Timing is without the use of the programmable clock manager (PCM).
This clock delay is for a fully routed clock tree that uses the ExpressCLK network. It includes both the input buffer delay, the clock routing to the
→
PIO CLK input, the clock Q of the FF, and the delay through the output buffer. The given timing requires that the input clock pin be located at
one of the six ExpressCLK inputs of the device, and that a PIO FF be used.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
CLKCNTRL
ECLK
ECLK
5-4846(F).a
Figure 76. ExpressCLK to Output Delay
Lucent Technologies Inc.
125
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