Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
UEND_SET
RDS_HLD
CS_HLD
CS_SET
RW_SET
A_SET
A_HLD
RW_HLD
RDS_SET
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
RDA_DEL
RDA_HLD
D[7:0]
MPI_STRB (TS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
TA_DELZ
TA_DEL
TA_DEL
BI_DEL
MPI_ACK (TA)
MPI_BI (BI)
BI_DEL
BI_DELZ
5-5832(F).c
Figure 69.
MPI PowerPC Internal Read Timing
CS_SET
RW_SET
A_SET
WD_HLD
CS_HLD
RW_HLD
A_HLD
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
WD_SET
D[7:0]
MPI_STRB (TS)
UA[3:0]
UA_DEL
URDWR_DEL
URDWRN
TA_DELZ
TA_DEL
BI_DEL
TA_DEL
BI_DEL
MPI_ACK (TA)
MPI_BI (BI)
BI_DELZ
5-5840(F).e
Figure 70.
MPI PowerPC Internal Write Timing
118
Lucent Technologies Inc.