Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
.
Table 56 OR3Cxx General System Clock (SCLK) to Output Delay (Pin-to-Pin)
<
<
<
<
<
DD
A
DD
A
L
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
T
+85 °C; C = 50 pF.
<
<
<
DD
A
A
T
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
+85 °C;
L =
C
50 pF.
Speed
Description
Device
Unit
-4
-5
-6
-7
J
DD
(T = 85 °C, V = min)
Min Max Min Max Min Max Min Max
Output On Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)
→
Clock Input Pin (mid-PIC) OUTPUT Pin (Fast) OR3T20
—
—
—
—
—
—
—
14.91
15.71
—
—
—
—
—
—
11.35
11.63
12.17
12.80
13.69
—
—
—
—
—
7.74
7.93
8.28
8.66
9.24
—
—
—
—
—
6.10 ns
6.27 ns
6.59 ns
6.95 ns
7.49 ns
OR3T30
OR3C/T55
OR3C/T80
OR3T125
→
Clock Input Pin (mid-PIC) OUTPUT Pin
(Slewlim)
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
17.34
18.14
—
—
—
—
—
—
13.34
13.62
14.16
14.79
15.68
—
—
—
—
—
8.42
8.60
8.95
9.34
9.91
—
—
—
—
—
6.63 ns
6.80 ns
7.12 ns
7.48 ns
8.02 ns
→
Clock Input Pin (mid-PIC) OUTPUT Pin
(Sinklim)
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
18.70
19.51
—
—
—
—
—
—
14.69
14.97
15.51
16.14
17.03
—
—
—
—
—
13.26
13.45
13.80
14.18
14.76
—
—
—
—
—
11.37 ns
11.54 ns
11.86 ns
12.22 ns
12.76 ns
Additional Delay if Non-mid-PIC Used as Clock
Pin
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
0.41
0.63
—
—
—
—
—
—
0.16
0.20
0.36
0.55
1.11
—
—
—
—
—
0.18
0.21
0.37
0.57
1.05
—
—
—
—
—
0.17 ns
0.20 ns
0.35 ns
0.55 ns
1.02 ns
Output Not on Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)
Additional Delay if Output Not on Same Side as
Input Clock Pin
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
0.41
0.63
—
—
—
—
—
—
0.16
0.20
0.36
0.55
1.11
—
—
—
—
—
0.18
0.21
0.37
0.57
1.05
—
—
—
—
—
0.17 ns
0.20 ns
0.35 ns
0.55 ns
1.02 ns
Note:
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the
→
PIO CLK input, the clock Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not
used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that a PIO FF be
ORCA
used. For clock pins located at any other PIO, see the results reported by
Foundry.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
SCLK
5-4846(F)
Figure 78. System Clock to Output Delay
Lucent Technologies Inc.
127