Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
FDBK–DEL
PFU
F[7:0]
F4_DEL
LUT
8
4
KZ[3:0]
F[6, 4,
2, 0]
F5–DEL
LUT
KZ[3:0], F5[A:D]
F4_DEL/
F5_DEL
LUT
F[7:0]
F4_DEL/
LUT
KZ[3:0]
SWL2_DEL
F4_DEL/
F5_DEL
LUT
F[7:0]
OMUX_DEL
O[9:0]
F4_DEL/
F5_DEL
LUT
F4_DEL/
LUT
KZ[3:0]
SWL3_DEL
F4_DEL/
F5_DEL
LUT
F[7:0]
F4_DEL/
F5_DEL
LUT
F5[A:D]
SWL2F5_DEL
F4_DEL/
F5_DEL
LUT
F[7:0]
F4_DEL/
F5_DEL
LUT
F4_DEL/
F5_DEL
LUT
F5[A:D]
SWL3F5_DEL
Note: See Table 46 for an explanation of FDBK_DEL and OMUX_DEL.
5-5751(F)
Figure 64. Combinatorial PFU Timing
Lucent Technologies Inc.
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