Advance Data Sheet
March 2001
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Electrical Characteristics (continued)
Table 7. Transmitter Electrical I/O Characteristics (TC = 0 °C to 65 °C, VCC = 3.3 V ± 5%) (continued)
Parameter
Symbol
Logic
Min
Typ
Max
Unit
Phase Error5:
PHERR
LVPECL
Output High, VOH
Output Low, VOL
VCC – 1.2
VCC – 2.2
—
—
VCC – 0.65
VCC – 1.5
V
V
Line Loopback Enable:
Active-low:
LLOOP
LVTTL
LVTTL
Input High, VIH
Input Low, VIL
2.0
0
—
—
VCC + 1.0
0.8
V
V
Diagnostic Loopback Enable:
Active- low:
DLOOP
Input High, VIH
Input Low, VIL
2.0
0
—
—
VCC + 1.0
0.8
V
V
Parallel Output Clock6:
PCLKP/N
Output High, VOH
Output Low, VOL
Differential Voltage Swing, ∆VDIFF
S-E Voltage Swing, ∆VSINGLE
Differential VCC – 1.15
LVPECL VCC – 1.95
—
—
—
—
VCC – 0.6
VCC – 1.45
1900
V
V
mV
mV
800
400
950
1. 20% to 80%.
2. Internally biased and ac-coupled.
3. The transmitter is normally enabled and only requires an external voltage to disable.
4. The WDEA alarm becomes active when the optical wavelength deviates from the nominal center wavelength by more than 100 pm.
5. Set at 500 mV at nominal optical output power. Provides linear PO tracking (–3 dB = 250 mV, +3 dB = 1000 V).
6. Terminated into 200 Ω to GND and 100 Ω line-to-line.
Table 8. Receiver Electrical I/O Characteristics (Tc = 0 °C to 65 °C, Vcc = 3.3 V ± 5%)
Parameter
Symbol
Logic
Min
Typ
Max
Unit
Parallel Output Clock:
Output High, VOH
Output Low, VOL
POCLKP/N
Differential
LVPECL
VCC – 1.3
VCC – 2.0
—
—
VCC – 0.7
VCC – 1.4
V
V
POCLk Duty Cycle
—
—
40
—
60
%
Output Data Signal Levels1:
Output High, VOH
Output Low, VOL
RxQ[0:15]P/N Differential
LVPECL
VCC – 1.3
VCC – 2.0
VCC – 0.7
VCC – 1.4
—
—
V
V
RxQ[0:15] Rise/Fall Time2
—
—
—
—
1.0
ns
Frame Pulse:
Output High, VOH
Output Low, VOL
FP
LVPECL
VCC – 1.3
VCC – 2.0
VCC – 0.7
VCC – 1.4
—
—
V
V
Loss-of-Signal Output:
Output High, VOH
Output Low, VOL
LOS
LVTTL
2.4
0
—
—
VCC
0.4
V
V
Out-of-Frame Input:
Input High, VIH
Input Low, VIL
OOF
LVTTL
LVTTL
V
V
2.0
0.0
—
—
TTL VCC + 1.0
0.8
Frame Enable Input
Input High, VIH
Input Low, VIL
FRAMEN
2.0
0.0
—
—
TTL VCC + 1.0
0.8
V
V
1. Terminated into 330 Ω to ground.
2. 20% to 80%, 330 Ω to ground.
17
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
