Data Sheet
March 2001
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Timing Characteristics
(continued)
EXTRINSIC PROPAGATION DELAY, t
P
(ns)
7
6
5
4
t
PLH
(TYP)
3
2
t
PHL
(TYP)
1
0
0
25
50
75
100
125
150
175 200
LOAD CAPACITANCE, C
L
(pF)
12-3462(F)
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to the external capacitance and the intrinsic delay of the device.
Figure 2. Typical Extrinsic Propagation Delay Versus Load Capacitance at 25 °C
INPUT
TRANSITION
2.4 V
1.5 V
0.4 V
t
P1
t
P2
V
OH
OUTPUTS
V
OL
t
PHH
OUTPUT
t
PLL
V
OH
(V
OH
+ V
OL
)/2
V
OL
OUTPUT
t
PHL
OUTPUT
t
PLH
V
OH
(V
OH
+ V
OL
)/2
V
OL
80%
20%
t
tLH
80%
20%
t
tHL
V
OH
V
OL
12-2677(F)
Figure 3. Driver Propagation Delay Timing
Agere Systems Inc.
7
AGERE [ AGERE SYSTEMS ]
