Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Timing Characteristics
(continued)
2.4 V
1.5 V
0.4 V
t
P1
OUTPUTS
V
OL
t
PHH
OUTPUT
t
PLL
V
OH
(V
OH
+ V
OL
)/2
V
OL
t
P2
V
OH
INPUT
TRANSITION
OUTPUT
t
PHL
OUTPUT
t
PLH
V
OH
(V
OH
+ V
OL
)/2
V
OL
80%
20%
t
tLH
80%
20%
t
tHL
V
OH
V
OL
12-2677F
Figure 2. Driver Propagation-Delay Timing
E1*
3.0 V
1.3 V
0.0 V
E2
†
3.0 V
1.3 V
0.0 V
t
PHZ
t
PZH
V
OH
V
OL
+ 0.2 V
V
OL
V
OL
– 0.1 V
OUTPUT
OUTPUT
t
PLZ
* E2 = 1 while E1 changes state.
† E1 = 0 while E2 changes state.
Note: In the third state, both outputs (i.e., OUTPUT and OUTPUT) are 0.2 V below the low state.
t
PZL
V
OL
V
OL
– 0.1 V
12-2268.dC
Figure 3. Driver Enable and Disable Timing for a High Input
6
Agere Systems Inc.