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ATTL7583CAJ-D 参数 Datasheet PDF下载

ATTL7583CAJ-D图片预览
型号: ATTL7583CAJ-D
PDF下载: 下载PDF文件 查看货源
内容描述: 线卡接入交换机 [Line Card Access Switch]
分类和应用: 电信集成电路光电二极管
文件页数/大小: 20 页 / 470 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
February 2001  
L7583A/B/C/D Line Card Access Switch  
Application (continued)  
Table 16. Truth Table for L7583A/B  
INRING  
INTESTin INTESTout  
TSD  
TESTin  
Switches Switches  
Break  
Ring Test  
Switches  
Ring  
TESTout  
Switches Switches  
0 V  
0 V  
0 V  
5 V  
5 V  
0 V  
5 V  
5 V  
0 V  
0 V  
5 V  
0 V  
5 V  
5 V  
0 V  
5 V  
0 V  
5 V  
0 V  
0 V  
0 V  
5 V  
5 V  
5 V  
5 V/Float1  
5 V/Float1  
5 V/Float1  
5 V/Float1  
5 V/Float1  
5 V/Float1  
5 V/Float1  
5 V/Float1  
0 V2  
Off  
Off  
On  
Off  
Off  
On  
Off  
Off  
Off  
On  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
On  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
On  
Off  
Off  
Off  
Off  
Off  
Off3  
On4  
Off5  
Off6  
Off7  
On8  
Off9  
Off9  
Off9  
Don’t  
Care  
Don’t  
Care  
Don’t  
Care  
1. If TSD = 5 V, the thermal shutdown mechanism is disabled. If TSD is floating, the thermal shutdown mechanism is active.  
2. Forcing TSD to ground overrides the logic input pins and forces an all OFF state.  
3. Idle/Talk state.  
4. TESTout state.  
5. TESTin state  
6. Power ringing state.  
7. Ringing generator test state.  
8. Simultaneous TESTout and TESTin state.  
9. All OFF state.  
A parallel in/parallel out data latch is integrated into the L7583A/B. Operation of the data latch is controlled by the  
logic level input pin LATCH. The data input to the latch is the INPUT pin of the L7583A/B, and the output of the data  
latch is an internal node used for state control.  
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from  
INPUT, through the data latch to state control. Any changes in INPUT will be reflected in the state of the switches.  
When the LATCH control pin is at logic 1, the data latch is active—the L7583A/B will no longer react to changes at  
the INPUT control pin. The state of the switches is now latched; that is, the state of the switches will remain as they  
were when the LATCH input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT  
as long as LATCH is held high.  
Note that the TSD input is not tied to the data latch. TSD is not affected by the LATCH input. TSD input will override  
state control via INPUT and LATCH.  
16  
Lucent Technologies Inc.