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1417G5 参数 Datasheet PDF下载

1417G5图片预览
型号: 1417G5
PDF下载: 下载PDF文件 查看货源
内容描述: NetLight 1417G5和1417H5型ATM / SONET / SDH收发器,时钟恢复 [NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery]
分类和应用: 异步传输模式ATM时钟
文件页数/大小: 12 页 / 151 K
品牌: AGERE [ AGERE SYSTEMS ]
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NetLight
1417G5 and 1417H5-Type
ATM/SONET/SDH Transceivers with Clock Recovery
Data Sheet
January 2000
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Supply Voltage
Operating Case Temperature Range
Storage Case Temperature Range
Lead Soldering Temperature/Time
Operating Wavelength Range
Symbol
V
CC
T
C
T
stg
λ
Min
0
–40
–40
1.1
Max
3.6
85
85
250/10
1.6
Unit
V
°C
°C
°C/s
nm
Pin Information
TX
20 19 18 17 16 15 14 13 12 11
20-PIN MODULE - TOP VIEW
RX
1 2 3 4 5 6 7 8 9 10
1-967(F).b
Figure 1. 1417G5 and 1714H5 Transceivers, 20-Pin Configuration, Top View
Table 1. Transceiver Pin Descriptions
Pin
Number
MS
Symbol
Name/Description
Receiver
Mounting Studs.
The mounting studs are provided for transceiver mechani-
cal attachment to the circuit board. They may also provide an optional con-
nection of the transceiver to the equipment chassis ground.
Photodetector Bias.
This lead supplies bias for the PIN photodetector diode.
Logic
Family
NA
MS
1
2
3
4
5
6
7
8
9
10
2
Photode-
tector Bias
Receiver Signal Ground.
V
EER
Receiver Signal Ground.
V
EER
Received Recovered Clock Out.
The rising edge occurs at the rising edge of
CLK–
the received data output. The falling edge occurs in the middle of the received
data bit period.
Received Recovered Clock Out.
The falling edge occurs at the rising edge
CLK+
of the received data output. The rising edge occurs in the middle of the
received data bit period.
Receiver Signal Ground.
V
EER
Receiver Power Supply.
V
CCR
Signal Detect.
SD
Normal operation: logic one output.
Fault condition: logic zero output.
Received DATA Out.
No internal terminations will be provided.
RD–
Received DATA Out.
No internal terminations will be provided.
RD+
NA
NA
NA
PECL
PECL
NA
NA
LVTTL
PECL
PECL
Agere Systems Inc.