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CT1815FP 参数 Datasheet PDF下载

CT1815FP图片预览
型号: CT1815FP
PDF下载: 下载PDF文件 查看货源
内容描述: 为MIL -STD - 1397 D型CT1815 10MHz的低电平的串行接口 [CT1815 10MHz Low Level Serial Interface for MIL-STD-1397 Type D]
分类和应用:
文件页数/大小: 7 页 / 85 K
品牌: AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
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Functional Description and Pinout  
Pin  
#
Load or  
Drive  
Pin Name  
Function  
1
2
3
No connection  
No connection  
XFMR secondary/  
RX data input  
Transmitter-receiver I/O pin  
4
5
6
7
8
9
Test Point  
Test Point  
Test Point  
-5 Volts  
No connection permitted  
No connection permitted  
No connection permitted  
R strobe  
Low level disables receiver  
3 S loads  
X
Power management  
input  
Controls transmitter power consumption in conjunction with pin 10 1 S load  
10 Encoder enable  
11 Case/signal GND  
12 Case/signal GND  
Controls transmitter power consumption in conjunction with pin 9 1 S load  
13 Decoded data  
envelope  
High after reception of first half bit; goes low after reception of last 4 S drive  
half bit (normally low in inactive state)  
14 TP3 test point  
15 TP1 test point  
16 TP2 test point  
17 -5 Volts  
Alignment point: no electrical connection permitted  
Alignment point: no electrical connection permitted  
Alignment point: no electrical connection permitted  
18 TP4 test point  
Alignment point: no electrical connection permitted  
19 Clock  
Reconstructed clock; one clock pulse per input bit received  
3 S drive  
3 S drive  
R
20 No connection  
21 Decoded Data  
22 No connection  
23 +5 volts  
NRZ reconstructed data. Sampled on clock rising edge  
R
R
24 +5 volts  
25 10 MHz encoder shift One cycle required per data bit. Must be high in first half of bit cell 1 S load  
clock  
26 NRZ serial input data Serial input to be Manchester encoded with the 20 MHz gated CK 1 S load  
27 Encode envelope  
Must be high to enable transmission; must go low before reception 1 S load  
of last 20 MHz positive edge to complete transmission  
28 20 MHz gated clock  
(encoder)  
Each bit to be encoded requires two positive edges of the 20 MHz 1 S load  
CK. These edges must occur at 25ns and 75ns into the bit cell.  
The end of transmission requires an additional edge in conjunction  
with a logic low on the encode envelope. t , t < 5nsec.  
R
F
29 Master reset  
Logic low resets encoder  
2 S load  
reset pulse <15 nsec  
30 No connection  
31 No connection  
32 XFMR secondary/  
RX DATA input  
Transmitter-Receiver I/O pin  
33 XFMR secondary  
Secondary isolated winding, same phase as outer conducter  
Transformer lead for connection to outer conductor of tri-axial  
34 XFMR primary/  
TX DATA output  
5
Aeroflex Circuit Technology  
SCDCT1815 REV A 6/12/98 Plainview NY (516) 694-6700