ACT5230
32-Bit Superscaler Microprocessor
Features
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Full militarized QED RM5230 microprocessor
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
133 and 150 MHz operating frequency – Consult
Factory for latest speeds
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228 Dhrystone2.1 MIPS
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SPECInt95 4.2 SPECfp95 4.5
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100,
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High-performance floating point unit
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Single
cycle repeat rate for common single precision
operations and some double precision operations
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Two cycle repeat rate for double precision multiply and
double precision combined multiply-add operations
Single cycle repeat rate for single precision combined
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multiply-add operation
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System interface optomized for embedded
applications
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32-bit
MIPS IV instruction set
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Floating
system interface lowers total system cost with up to
87.5 MHz operating frequency
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High performance write protocols maximize uncached
write bandwidth
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Operates at processor clock divisors 2 through 8
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5V tolerant I/O's
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IEEE 1149.1 JTAG boundary scan
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point multiply-add instruction increases
performance in signal processing and graphics
applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
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Embedded application enhancements
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Specialized
Integrated on-chip caches
instruction - 2 way set associative
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16KB data - 2 way set associative
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Early restart on data cache misses
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16KB
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DSP integer Multiply-Accumulate instruction
and 3 operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
Fully static CMOS design with power down logic
Standby reduced power mode with WAIT instruction
2.5 Watts typical with less than 70 mA standby current
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128-pin Power Quad-4 package (F22),
Consult Factory for
package configuration
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Integrated memory management unit
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Fully
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48
associative joint TLB (shared by I and D translations)
dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
Block Diagram
Data Set A
Store Buffer
Phase Lock Loop
Instruction Set A
Data Tag A
DTLB Physical
Data Tag B
Instruction Select
Sys AD
Integer Instruction Register
Write Buffer
Read Buffer
Data Set B
Instruction Tag B
DBus
FPIBus
Control
Tag
Floating-point
Register File
Floating point Control
Unpacker/Packer
Aux Tag
Load Aligner
Joint TLB
Integer Register File
Integer/Address Adder
Integer Control
Coprocessor 0
DVA
System/Memory
Control
IVA
Data TLB Virtual
IntIBus
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Set B
FP Instruction Register
Floating-point
MAdd, Add, Sub,Cvt
Div, SqRt
Shifter/Store Aligner
Logic Unit
ABus
PC Incrementer
Branch Adder
Instruction TLB Virtual
Integer Multiply, Divide
Program Counter
Preliminary
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5230 REV 1 12/22/98
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
