ACT5260
64-Bit Superscaler Microprocessor
Features
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Full militarized QED RM5260 microprocessor
Dual Issue superscalar QED RISCMark
™
- can issue one
integer and one floating-point instruction per cycle
microprocessor - can issue one integer and one
floating-point instruction per cycle
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100, 133 and 150MHz frequency (200MHz future option)
Consult Factory for latest speeds
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260 Dhrystone2.1 MIPS
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SPECInt95 4.8. SPECfp95 5.1
High performance system interface compatible with R4600,
R4700 and R5000
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64-bit multiplexed system address/data bus for optimum
price/performance up to 100 MHz operating frequency
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High performance write protocols maximize uncached
write bandwidth
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Operates at input system clock multipliers of 2 through 8
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5V tolerant I/O's
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IEEE 1149.1 JTAG boundary scan
Integrated on-chip caches - up to 3.2GBps internal data rate
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16KB instruction - 2 way set associative
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16KB data - 2 way set associative
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Pipeline restart on first double for data cache misses
Integrated memory management unit
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Fully associative joint TLB (shared by I and D translations)
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48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
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Embedded supply de-coupling capacitors and Pll filter
components
High-performance floating point unit - up to 400 MFLOPS
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Single cycle repeat rate for common single precision
operations and some double precision operations
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Two cycle repeat rate for double precision multiply and
double precision combined multiply-add operations
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Single cycle repeat rate for single precision combined
multiply-add operation
MIPS IV instruction set
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Floating point multiply-add instruction increases
performance in signal processing and graphics
applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
Embedded application enhancements
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Specialized DSP integer Multiply-Accumulate instruction
and 3 operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
Fully static CMOS design with power down logic
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Standby reduced power mode with WAIT instruction
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5 Watts typical at 3.3V, less than 175 mwatts in Standby
208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
(Consult Factory)
179-pin PGA package (Future
Product)
(P10)
BLOCK DIAGRAM
Phase Lock Loop
Data Set A
Data Tag A
Store Buffer
DTLB Physical
Data Tag B
Instruction Select
Sys AD
Instruction Set A
Integer Instruction Register
Write Buffer
Read Buffer
Data Set B
Instruction Tag B
DBus
FPIBus
Control
Tag
Floating-point
Register File
Unpacker/Packer
Floating point Control
Aux Tag
Load Aligner
Joint TLB
Integer Register File
Integer/Address Adder
Integer Control
Coprocessor 0
DVA
System/Memory
Control
IVA
Data TLB Virtual
IntIBus
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Set B
FP Instruction Register
Floating-point
MAdd, Add, Sub,Cvt
Div, SqRt
Shifter/Store Aligner
Logic Unit
ABus
PC Incrementer
Branch Adder
Instruction TLB Virtual
Integer Multiply, Divide
Program Counter
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5260 REV A 3/29/99
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
