ACT5231
32-Bit Superscaler Microprocessor
Features
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Full militarized QED RM5231 microprocessor
Pinout compatible with popular RM5230 with split power sup
plies (2.5V and 3.3V)
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
150 and 200 MHz operating frequencies – Consult Factory for
latest speeds
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325 Dhrystone2.1 MIPS
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SPECInt95 5.0, SPECfp95 5.25
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133,
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High-performance floating point unit
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532
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MFLOPS single-precision performance
cycle repeat rate for common single precision opera-tions
and some double precision operations
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Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
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Single cycle repeat rate for single precision combined multiply-
add operation
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Single
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MIPS IV instruction set
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Floating
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System interface optimized for embedded applications
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32-bit
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High
system interface lowers total system cost
performance write protocols maximize uncached write
bandwidth with 600 MB per second peak throughput
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Operates at processor clock divisors 2, 2.5, 3, 3.5,4, 4.5, 5, 6, 7, 8, 9
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IEEE 1149.1 JTAG boundary scan
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point multiply-add instruction increases performance in
signal processing and graphics applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
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Embedded application enhancements
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Specialized
Integrated on-chip caches
instruction and 32KB data - 2 way set associative and per
set locking
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Pipeline restart on first double for data cache misses
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32KB
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DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
Fully static CMOS design with power down logic
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Standby
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2.7
reduced power mode with WAIT instruction
W typical power @ 200MHz
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2.5V core with 3.3V IO’s
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Integrated memory management unit
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Fully
associative joint TLB (shared by I and D translations)
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48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
128-pin Power Quad-4 package (F22),
Consult Factory for
package configuration
Block Diagram
Preliminary
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5231 REV 1 12/22/98
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
