A(18:0)
t
AVAV
2
En
t
AVWH
t
ETWH
Wn
t
AVWL
Q(7:0)
t
WLQZ
D(7:0)
Assumptions:
1. G < V
IL
(max). If G > V
IH
(min) then Qn(8:0) will be
in three-state for the entire cycle.
2. G high for t
AVAV
cycle.
APPLIED DATA
t
WHWL
t
WHAX
t
WLWH
t
WHQX
t
DVWH
t
WHDX
Figure 5a . SRAM Write Cycle 1: Write Enable - Controlled Access
t
AVAV
3
A(18:0)
t
AVET
t
ETEF
t
EFAX
En
or
t
AVET
En
t
ETEF
t
WLEF
APPLIED DATA
t
EFAX
Wn
D(7:0)
t
WLQZ
Q(7:0)
t
DVEF
t
EFDX
Assumptions & Notes:
1. G < V
IL
(max). If G > V
IH
(min) then Q(7:0) will be in three-state for the entire cycle.
2. Either En scenario above can occur.
3. G high for t
AVAV
cycle.
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
9