Table 9: External I/O Reset State
External I/O
Address/Data Bus (AD15:0)
ALE
ADV
RD
WR
WRL
Port 0 (P0.0-P0.3; P0.6)
ECB(4:0)
Port 0 (P0.4 and P0.5)
Port 0 (P0.7)
EXTINT
NMI
HSI.0
T2RST
HSI.1
T2CLK
HSI.2/HSO.4
HSI.3/HSO.5
HSO.0 through HSO.3
Port 1 (P1.0-P1.7)
PWM1; PWM2;
BREQ; HLDA; HOLD
Port 2 (P2.0)
TXD
Port 2 (P2.1)
RXD
Port 2 (P2.2)
EXTINT
Port 2 (P2.3)
T2CLK
Port 2 (P2.4)
T2RST
I/O Function After Reset
Address/Data Bus
ALE
RD
WR
[P0.0-P0.3; P0.6] and
ECB(4:0)
P0.4 and P0.5
P0.7
NMI
HSI.0
HSI.1
Undefined
Undefined
HSO.0-HSO.3
P1.0-P1.7
Undefined Inputs
1
Undefined Input
1
Pulled Down
Disabled Input
1
Disabled Input
1
Disabled I/O
1
Disabled I/O
1
Pulled Down
Pulled Up
Undefined Inputs
1
Undefined Input
1
Pulled Down
Disabled Input
1
Disabled Input
1
Disabled I/O
1
Disabled I/O
1
Driven Low
Outputs
Pulled Up
I/O State During
Reset
Pulled High
Pulled High
Pulled High
Pulled High
Undefined Inputs
1
I/O State After Reset
Driven Output
Driven Output
Driven Output
Driven Output
Undefined I/O
1,2
TXD
RXD
P2.2 and EXTINT
P2.3 and T2CLK
P2.4
Pulled Up
Undefined Input
1
Undefined Input
1
Undefined Input
1
Undefined Input
1
Driven High
Output
Undefined Input
1
Undefined Input
1
Undefined Input
1
Undefined Input
1
9
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
