Table 10: 68-lead Flat Pack Pin Descriptions
QFP Pin#
I/O
Name
Active
Description
34
TDO
HSO.2
---
High Speed Output Module, output pin 2. The HSO.2 pin is a
dedicated output for the HSO module.
35
36
TDO
GND
HSO.3
VSS
---
---
High Speed Output Module, output pin 3. The HSO.3 pin is a
dedicated output for the HSO module.
Digital circuit ground (0V). There are 4 VSS pins, all of which
must be connected and one additional recommended VSS con-
nection.
37
38
TI
EDACEN
Low
EDAC Enable. Asserting the EDACEN signal activates the
error detection and correction engine. This causes the
UT80CRH196KD to include ECB(5:0) as the EDAC check bit
pins in all external memory cycles.
TUQ
TUQ
P2.7
---
Port 2 Pin 7. A quasi-bidirectional port pin that is read and writ-
ten at location 10h of HWindow 0.
T2CAPTURE
High
Timer 2 Capture. A rising edge on this pin loads the value of
Timer 2 into the T2CAPTURE register, and generates a Timer 2
Capture interrupt (INT11, 2036h). Assert the T2CAPTURE sig-
nal for at least 2 state times to guarantee acknowledgment by the
interrupt controller. Using INT_Mask1.3 controls whether or not
a rising edge causes an interrupt.
39
TDO
TDO
P2.5
---
---
Port 2 Pin 5. An output only port pin that is written at location
10h of HWindow 0.
Setting IOC1.0 = 0 enables the P2.5 function of pin 39.
PWM0
Pulse Width Modulator (PWM) Output 0. The output signal
will be a waveform whose duty cycle is programmed by the
PWM0_CONTROL register, and the frequency is selected by
IOC2.2.
Setting IOC1.0 = 1 enables the PWM0 function of pin 39.
402
TUO
TUO
WR
Low
Low
Write. The WR signal indicates that an external write is occur-
ring. Activation of this signal only occurs during external mem-
ory writes.
Setting CCR.2 = 1 enables the WR function of pin 40.
WRL
Write Low. The WRL signal is activated when writing the low
byte of a 16-bit wide word, and is always asserted for 8-bit wide
memory writes.
Setting CCR.2 = 0 enables the WRL function of pin 40.
19
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