Table 10: 68-lead Flat Pack Pin Descriptions
QFP Pin#
I/O
Name
Active
Description
7
TI
P0.2
---
Port 0 Pin 2. An input only port pin that is read at location 0Eh
in HWindow 0.
ECB11
TB
---
EDAC Check Bit 1. Asserting the EDACEN pin will cause the
error detection and correction engine to pass the EDAC Check
Bit 1 through pin 7 of the UT80CRH196KD.
8
9
TI
P0.6
---
---
Port 0 Pin 6. An input only port pin that is read at location 0Eh
in HWindow 0.
ECB01
TB
EDAC Check Bit 0. Asserting the EDACEN pin will cause the
error detection and correction engine to pass the EDAC Check
Bit 0 through pin 8 of the UT80CRH196KD.
TI
TI
P0.7
---
Port 0 Pin 7. An input only port pin that is read at location 0Eh
in HWindow 0.
EXTINT
High
External Interrupt. Setting IOC1.1 = 1 enables pin 9 as the
source for the external interrupt EXTINT. A rising edge on this
pin will generate EXTINT (INT07, 200Eh). Assert EXTINT for
at least 2 state times to ensure acknowledgment by the interrupt
controller.
During Power Down mode, asserting EXTINT places the chip
back into normal operation, even if EXTINT is masked.
10
11
12
TI
TI
P0.5
P0.4
VSS
---
---
---
Port 0 Pin 5. An input only port pin that is read at location 0Eh
in HWindow 0.
Port 0 Pin 4. An input only port pin that is read at location 0Eh
in HWindow 0.
GND
Digital circuit ground (0V). There are 4 VSS pins, all of which
must be connected and one additional recommended VSS con-
nection.
13
14
PWR
GND
VDD
---
---
Digital supply voltage (+5V). There are 2 VDD pins, both of
which must be connected.
VSS
Digital circuit ground (0V). There are 4 VSS pins, all of which
must be connected and one additional recommended VSS con-
nection.
14
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
