5.0 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
V
DD
= 5.0V
±
10%; TA = -55°C < T
C
< +125°C)
SYMBOL
V
IL
V
IH
V
IH1
V
OL
PARAMETER
Low-level Input Voltage
High-level Input Voltage
(except XTAL, RST)
High-level Input Voltage
(XTAL, RST)
Low-level Output Voltage
1
(Ports 1, 2 and 3)
I
OL
= 100µA
I
OL
= 1.6mA
I
OL
= 3.5mA
V
OL1
Low-level Output Voltage
1,2
(Port 0, ALE, PSEN, PROG)
I
OL
= 200µA
I
OL
= 3.2mA
I
OL
= 7.0mA
V
OH
High-level Output Voltage
3
(Ports 1, 2, and 3
ALE and PSEN)
I
OH
= -10µA
4.2
2.0
3.85
0.3
0.45
1.0
0.3
0.45
1.0
CONDITION
MINIMUM
MAXIMUM
0.8
UNIT
V
V
V
V
V
V
V
V
V
V
I
OH
= -30µA
I
OH
= -60µA
V
OH1
High-level Output Voltage
(Port 0 in External Bus Mode)
I
OH
= -200µA
I
OH
= -3.2mA
I
OH
= -7.0mA
I
IL
I
IL
I
LI
I
LI
C
IO4
I
DD
Logical 0 Input Current
(Ports 1, 2, and 3)
Logical 0 Input Current
(XTAL 1)
Input Leakage Current
(Port 0)
Input Leakage Current
(XTAL1)
Pin Capacitance
Power Supply Current:
V
IN
= 0.0V
V
CC
= 5.5V
V
IN
= 0.0V
V
CC
= 5.5V
V
IN
= 0.0V or V
CC
V
CC
= 5.5V
V
IN
= 0.0V or V
CC
V
CC
= 5.5V
@ 1MHZ, 25°C
@16MHz
@20 MHz
3.8
3.0
4.2
3.8
3.0
-50
-65
-65
±25
±65
±65
15
95
120
V
V
V
V
V
µA
µA
µA
µA
pF
mA
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883.
1. Under steady state (non-transient) conditions, I
OL
must be limited externally as follows:
10mA
Maximum I
OL
per port pin:
Maximum I
OL
per 8-bit port-
Port 0: 26mA
Ports 1, 2, & 3: 15mA
Maximum total I
OL
for all output pins: 71mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OL
of ALE and ports 1 and 3. The noise is due to external bus
capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operations. In applications where capacitance loading
exceeds 100 pF, the noise pulse on the ALE may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a schmitt trigger or use an address latch
with a schmitt trigger strobe input.
3. Capacitive loading ports 0 and 2 cause the V
OH
on ALE and PSEN to drop below the VDD-0.3 specification when the address lines are stabilizing.
4. Capacitance measured for initial qualification or design changes which may affect the value.
8
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
