3.0 RADIATION HARDNESS
circuit density and reliability. For transient radiation hardness
and latchup immunity, UTMC builds all radiation-hardened
products on epitaxial wafers using an advanced twin-tub CMOS
process. In addition, UTMC pays special attention to power and
ground distribution during the design phase, minimizing dose-
rate upset caused by rail collapse.
TheUT69RH051 incorporates special design and layoutfeatures
which allow operation in high-level radiation environments.
UTMC has developed special low-temperature processing
techniques designed to enhance the total-dose radiation hardness
of both the gate oxide and the field oxide while maintaining the
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RADIATION HARDNESS DESIGN SPECIFICATIONS
Total Dose
1.0E6
20
rad(Si)
2
LET Threshold
MeV-cm /mg
2
Neutron Fluence
1.0E14
1E-4
n/cm
2
Saturated Cross-Section (1Kx8)
Single Event Upset
cm /device
2
1.3E-7
errors/device-day
1
2
LET>126
Single Event Latchup
MeV-cm /mg
Note:
1. Worst case temperature TA = +125°C.
2. Adams 90% worst case environment (geosynchronous).
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4.0 ABSOLUTE MAXIMUM RATINGS
(Referenced to V )
SS
SYMBOL
PARAMETER
DC Supply Voltage
LIMITS
UNITS
V
-0.5 to 7.0
V
DD
V
Voltage on Any Pin
-0.5 to V +0.3V
V
°C
I/O
DD
T
Storage Temperature
-65 to +150
STG
P
Maximum Power Dissipation
Maximum Junction Temperature
750
175
10
mW
°C
D
T
J
2
Θ
°C/W
mA
JC
Thermal Resistance, Junction-to-Case
DC Input Current
I
±10
I
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Test per MIL-STD-883, Method 1012.
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