A704
LAYOUT GUIDELINES
1. PCB Layout consideration：The hold-up capacitor C5 need closed by the VDD pin of the controller IC。
2. PCB Layout consideration: Please must put these components, (Cin1, Q1, R4, DF) & (Q1,704, R4,R7), as close as
possible to each other when in PCB placement ( refer to Fig-1, Fig-11 & Fig-12). An A704 DC-DC may not work
well if some of these components are placed far away from others.
3. When the MOSFET turned on, a spike, which is induced by the diode reverse recovery and by the output
capacitances of the MOSFET and diode, inevitably appears on the sensed signal. Inside A704, a leading edge
blanking time about 250nsec is introduced to avoid premature termination of MOSFET by the spike. Therefore,
only a small-value RC filter (e.g. 100ohm + 470pF) is required between the SENSE pin and RS.
4. A704 output stage is a totem pole driver stage that can directly drive MOSFET gate. It is also equipped with a
voltage clamping circuit to protect MOSFET from damage caused by undesirable over drive voltage. The output
voltage is clamped at 20Vmax. An external pull down resistor Rx in the range of 10k to 47k ohm is used to avoid
floating state of gate before startup. A gate drive resistor Rg in the range from several to several tens ohm is
recommended. This resistor limits the peak gate drive current and provides damping to prevent oscillations at the
MOSFET gate terminal.
Rg
VDD
Gate
CS
RF
GND
RS
CF
Rx
L
COUT
DF
Fig.10. Gate drive
5. The power stage ground and the controller loop ground in this circuit is different, therefore, the measurement
equipment need be isolated with device under test (DUT).
6. When output load is open/disconnect, the output voltage would increase the value of the over-voltage protection.
However, the start-up circuitry still charges energy to the output capacitor; Placed a dummy load in the range of
10k to 47k ohm in the output is recommended.
Contack Info:Samsun Zhang 13556850583 IC9898@163.com
Copyright © 2008 ADDtek Corp.
12
A704_V0.6 -- AUGUST 2008
ADDTEK [ ADDTEK CORP ]
