OP270
0
–1
PHASE SHIFT (Degrees)
FIVE-BAND LOW NOISE STEREO GRAPHIC EQUALIZER
SINGLE OP AMP.
CONVENTIONAL DESIGN
–2
–3
CASCADED
(TWO STAGES)
–4
–5
LOW PHASE ERROR
AMPLIFIER
–6
–7
0.001
The graphic equalizer circuit shown in Figure 14 provides 15 dB of
boost or cut over a 5-band range. Signal-to-noise ratio over a 20 kHz
bandwidth is better than 100 dB and referred to a 3 V rms input.
Larger inductors can be replaced by active inductors, but this
reduces the signal-to-noise ratio.
DIGITAL PANNING CONTROL
0.01
0.005
0.05
FREQUENCY RATIO (1/
0.1
)( /
T
)
0.5
1.0
Figure 15 uses a DAC8221, a dual 12-bit CMOS DAC, to pan
a signal between two channels. One channel is formed by the
current output of DAC A driving one-half of an OP270 in a
current-to-voltage converter configuration. The other channel is
formed by the complementary output current of DAC A, which
normally flows to ground through the AGND pin. This comple-
mentary current is converted to a voltage by the other half of the
OP-270, which also holds AGND at virtual ground.
Gain error due to mismatching between the internal DAC ladder
resistors and the current-to-voltage feedback resistors is elimi-
nated by using feedback resistors internal to the DAC8221. Only
DAC A passes a signal; DAC B provides the second feedback
resistor. With V
REF
B unconnected, the current-to-voltage converter,
using R
FB
B, is accurate and not influenced by digital data reach-
ing DAC B. Distortion of the digital panning control is less than
0.002% over the 20 Hz to 20 kHz audio range. Figure 16 shows
the complementary outputs for a 1 kHz input signal and a digital
ramp applied to the DAC data input.
DUAL PROGRAMMABLE GAIN AMPLIFIER
Figure 13. Phase Error Comparison
C1
0.47 F
V
IN
R1
47k
+
1/2
OP270E
–
C2
6.8 F
+
TANTALUM
C3
1 F
+
TANTALUM
C4
0.22 F
R4
1k
L1
1H
R6
1k
L2
600mH
R8
1k
L3
180mH
R10
1k
L4
60mH
R12
1k
L5
10mH
10kHz
3kHz
800Hz
200Hz
60Hz
R2
3.3k
+
1/2
OP270E
–
R13
3.3k
R14
100
V
OUT
R3
680
R5
680
R7
680
The dual OP270 and the DAC8221, a dual 12-bit CMOS
DAC, can be combined to form a space-saving dual program-
mable amplifier. The digital code present at the DAC, which is
easily set by a microprocessor, determines the ratio between the
internal feedback resistor and the resistance the DAC ladder
presents to the op amp feedback loop. Gain of each amplifier is
V
OUT
4096
=
–
V
IN
n
where n equals the decimal equivalent of the 12-bit digital code
present at the DAC. If the digital code present at the DAC
consists of all zeros, the feedback loop will open, causing the op
amp output to saturate. A 20 MW resistor placed in parallel with
the DAC feedback loop eliminates this problem with only a very
small reduction in gain accuracy.
R9
680
C5
0.047 F
R11
680
C6
0.022 F
Figure 14. 5-Band Low Noise Graphic Equalizer
–12–
REV. C
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