欢迎访问ic37.com |
会员登录 免费注册
发布采购

OP16AJMDA 参数 Datasheet PDF下载

OP16AJMDA图片预览
型号: OP16AJMDA
PDF下载: 下载PDF文件 查看货源
内容描述: 精密JFET输入运算放大器 [Precision JFET-Input Operational Amplifiers]
分类和应用: 运算放大器
文件页数/大小: 12 页 / 431 K
品牌: ADI [ ADI ]
 浏览型号OP16AJMDA的Datasheet PDF文件第4页浏览型号OP16AJMDA的Datasheet PDF文件第5页浏览型号OP16AJMDA的Datasheet PDF文件第6页浏览型号OP16AJMDA的Datasheet PDF文件第7页浏览型号OP16AJMDA的Datasheet PDF文件第8页浏览型号OP16AJMDA的Datasheet PDF文件第9页浏览型号OP16AJMDA的Datasheet PDF文件第10页浏览型号OP16AJMDA的Datasheet PDF文件第12页  
OP15/OP17  
2k  
0.1%  
TEST CIRCUITS  
+15V  
V+  
400⍀  
0.1%  
10V  
0V  
100k  
2
3
7
6
7
OP17  
2N4416  
100pF  
5
2
3
1k⍀  
0.1%  
1
4
6
4
3k⍀  
–15V  
V
OUT  
SUMMING  
NODE  
A
V
= –1  
5k⍀  
0.1%  
NOTE:V  
CAN BETRIMMEDWITH POTENTIOMETERS  
OS  
RANGING FROM 10kTO 1M. FOR MOST UNITS  
TCV WILL BE MINIMIZEDWHEN V IS ADJUSTED  
WITH A 100kPOTENTIOMETER  
OS  
OS  
SCOPE  
+15V  
2N4416  
Figure 3. Input Offset Voltage Nulling  
2k⍀  
2k⍀  
0.1%  
Figure 6. OP17 Settling Time Test Circuit  
+15V  
APPLICATION INFORMATION  
DynamicOperatingConsiderations  
2k⍀  
0.1%  
10V  
0V  
2
3
7
OP15  
4
6
As with most amplifiers, care should be taken with lead dress,  
component placement and supply decoupling in order to ensure  
stability. For example, resistors from the output to an input should  
be placed with the body close to the input to minimize “pick-up”  
and maximize the frequency of the feedback pole by minimizing  
the capacitance for the input to ground.  
2N4416  
5k⍀  
0.1%  
100pF  
3k⍀  
–15V  
V
OUT  
SUMMING  
NODE  
A
V
= –1  
5k⍀  
0.1%  
SCOPE  
A feedback pole is created when the feedback around any amplifier  
is resistive. The parallel resistance and capacitance from the input  
of the device (usually the inverting input) to ac ground set the  
frequency of this pole. In many instances the frequency of this  
pole is much greater than the expected, 3 dB frequency of the  
close-loop gain, and consequently there is negligible effect on  
stability margin. However, if the feedback pole is less than approxi-  
mately six times the expected 3 dB frequency, a lead capacitor  
should be placed from the output to the negative input of the op  
amp. T he value of the added capacitor should be such that the  
RC time-constant of this capacitor and the resistance it parallels  
is greater than, or equal to, the original feedback pole time is constant.  
+15V  
2N4416  
2k⍀  
Figure 4. OP15 Settling Time Test Circuit  
R1  
R2  
10k  
5k⍀  
C2  
30pF  
DIGITAL INPUTS  
+10V  
LSB  
MSB  
5
+15V  
7
R
6
7
8
9
10 11  
12  
REF  
5k  
B1 B2 B3 B4 B5 B6 B7 B8  
14  
15  
4
2
2
3
V
I
O
REF+  
6
DAC08E  
OP15F  
V
I
O
REF–  
V+  
V
= 0VTO 10V  
O
4
V–  
13  
C
C
V
LC  
3
16  
1
C1  
0.1F  
+15V  
–15V  
–15V  
Figure 5. Current-to-Voltage Amplifier Output  
REV. A  
–11–  
 复制成功!