Ultralow Offset Voltage
Operational Amplifier
OP07
FEATURES
PIN CONFIGURATION
Low VOS: 75 μV maximum
1
2
3
4
8
7
6
5
V
TRIM
–IN
+IN
V–
V
TRIM
OS
OS
OP07
Low VOS drift: 1.3 μV/°C maximum
Ultrastable vs. time: 1.5 μV per month maximum
Low noise: 0.6 μV p-p maximum
Wide input voltage range: 14 V typical
Wide supply voltage range: 3 V to 18 V
125°C temperature-tested dice
V+
OUT
NC
NC = NO CONNECT
Figure 1.
APPLICATIONS
Wireless base station control circuits
Optical network control circuits
Instrumentation
The wide input voltage range of ±±1 V minimum combined
with a high CMRR of ±06 dB (OP07E) and high input
Sensors and controls
Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements
Precision filters
impedance provide high accuracy in the noninverting circuit
configuration. Excellent linearity and gain accuracy can be
maintained even at high closed-loop gains. Stability of offsets
and gain with time or variations in temperature is excellent. The
accuracy and stability of the OP07, even at high gain, combined
with the freedom from external nulling have made the OP07 an
industry standard for instrumentation applications.
GENERAL DESCRIPTION
The OP07 is available in two standard performance grades. The
OP07E is specified for operation over the 0°C to 70°C range,
and the OP07C is specified over the −40°C to +85°C
temperature range.
The OP07 has very low input offset voltage (75 μV maximum for
OP07E) that is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external
nulling. The OP07 also features low input bias current (±4 nA for
the OP07E) and high open-loop gain (200 V/mV for the OP07E).
The low offset and high open-loop gain make the OP07
The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow
SOIC packages. For CERDIP and TO-99 packages and standard
microcircuit drawing (SMD) versions, see the OP77.
particularly useful for high gain instrumentation applications.
V+
7
1
1
R2B
R2A
(OPTIONAL
NULL)
R7
C1
8
1
R1B
R1A
Q19
R9
Q10
Q9
Q11
Q12
Q8
OUT
6
Q7
Q3 Q6
Q1
Q4
Q5
C3
R5
Q17
R3
R4
C2
Q27
Q26
Q25
R10
Q20
NONINVERTING
INPUT
Q16
Q15
3
2
Q23
Q24
Q21
Q22
INVERTING
INPUT
Q2
Q14
Q18
R8
Q13
R6
4
V–
1
R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE.
Figure 2. Simplified Schematic
Rev. D
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