AD5940
Data Sheet
V
V
VREF_2V5
AIN4_LPF0
BIAS0
ZERO0
LPDACSW0[3]
LPDACSW0[1]
SW12
SW13
LPBUF
RE0
OPEN: LPDACCON0[5] = 1
AND LPDACSW0[4] = 0
LPDACCON0[3]
12-BIT
SW15
+
–
PA
CE0
LPDAC0
V
ZERO0
SW2
6-BIT
LPREF
LPDACCON0[4]
SW3
SW8
LPDACSW0[2]
SW10
SW6
10kΩ
10kΩ
RE0
SE0
SW4
+
–
LPTIA0_P
_LPF0
SW11
R
LOAD
LPTIA
SW5
SW9
R
LPF
LPTIACON0
[12:10]
LPTIACON0
[15:13]
SW7
ADC
MUX
R
TIA
SW1
LPTIACON0
[9:5]
FORCE/SENSE
RC0_0
RC0_1
SW0
ADCVBIAS_CAP (1.11V)
VZERO0
TSWFULLCON[4]
T5
LPDACSW0[0]
1
HSTIA
SE0
TSWFULLCON[4]
T7
1
FOR DETAILS ON THE HSTIA, SEE THE HSTIA CIRCUITS CHAPTER OF THIS DOCUMENT.
Figure 19. Low Bandwidth Loop Switches
Rev. 0 | Page 36 of 130
ADI [ ADI ]
