TDM INPUT (HDR1)
3
NOT USED (S8)
2
3
EVAL-AD1896EB
DATA
TDM OUTPUT (HDR2)
DIRECT DIGITAL INPUT (HDR3)
3
BYPASS (S6)
3
3/5 IODV
DD
256
f
S
5V DV
DD
5V DV
DD
DATA
DATA
DATA
DIR
CS8414
3
I/F MODE
M/S MODE
3
4
RESET
3
RESET
Y1
33MHz
(3rd OT)
I/F MODE
3
3
3
DATA
TDM_IN
RESET
5V DV
DD
3.3V DV
DD
256
f
S
DIRECT DIGITAL OUTPUT (HDR5)
5V AV
DD
5V DV
DD
SPDIF IN (J1)
SPDIF OUT (J2)
DIT
CS8404A
SWITCH S2
ASRC
AD1896
I/F MODE
4
I/F MODE
3
OUTPUT
INTERFACE
PLD
MACH 4
TOSLINK
INPUT
INTERFACE
PLD
MACH 4
128
f
S
Figure 5. Evaluation Board Block Diagram
–8–
MUTE (S7)
SPDIF STATUS
3
2, 3
PROG DVDR
5V DV
DD
5V DV
DD
OSCILLATOR
3V/5V IODV
DD
256
f
S
768
f
S
2
512
f
S
256
f
S
128
f
S
256
f
S
256
f
S
AUDIO MODE
RESET
3
(DIT)
(DAC)
PRE-EMPHASIS
VERF
2
2
5V DV
DD
MODE
DATA
3
MUTE
RESET
DAC
5V AV
DD
2
OUTPUT INTERFACE
MODE (JP1)
(LJ/I2S/TDM/RJ)
OUTPUT
WORDLENGTH (JP1)
(16/18/20/24 BITS)
DAC LEFT (J6)
INPUT SIGNAL SOURCE (S1)
(DIR/DDI)
INPUT INTERFACE MODE (S3)
(LJ/I
2
S/RJ)
MASTER/SLAVE CLOCK MODE (S4)
AD1852
DAC RIGHT (J7)
15V INPUT
REGULATOR
ZEROL
(DDIO)
ZEROR
S5
RESET
RESET
GENERATOR
NOTES
DIGITAL DATA INTERFACE SIGNALS
1. /2 SCLK_0, LRCLK_0
2. /3 BCLK, LRCLK, SDATA
3. /4 MCLK, BCLK, LRCLK, SDATA
REV. 0
AD [ ANALOG DEVICES ]
