EVAL-AD1896EB
5V
U2
CLR
LD
ENT
ENP
MCLK
24.576MHz
CLK RCO
D0
D1
D2
D3
Q0
Q1
Q2
Q3
BCLK
12.288MHz
BCLK
LRCLK
MCLK
HEADER10
DDO DIRECT DIGITAL OUTPUT HEADER
J1
5V
74AC161
U3
CLR
LD
ENT
ENP
CLK RCO
D0
D1
D2
D3
Q0
Q1
Q2
Q3
LRCLK
192kHz
NOTES
1. REPLACE U15, 12.288MHz OSCILLATOR WITH 24.576MHz
2. SET S3, I/P IF MODE TO 1 FOR I
2
S
3. SET S4, MASTER/SLAVE MODE TO 7
4. JUMPER JP4, MCLK_SRCE PINS 1 AND 2
5. JUMPER JP1, O/P I/F MODE POSITIONS 1, 2, AND 4 FOR 24-BIT I
2
S OUTPUT
6. JUMPER JP2, SELECT POSITION 1 ONLY FOR 192kHz DAC OPERATION
7. SET S1 TO DIR
8. SET S2 TO SELECT COAX OR OPTICAL INPUT
74AC161
Figure 4. 192 kHz Clock Generator for AD1896EB
REV. 0
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